1/* $NetBSD: sunxi_codec.c,v 1.14 2021/05/05 20:58:03 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include "opt_ddb.h" 30 31#include <sys/cdefs.h> 32__KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.14 2021/05/05 20:58:03 jmcneill Exp $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/cpu.h> 37#include <sys/device.h> 38#include <sys/kmem.h> 39#include <sys/gpio.h> 40 41#include <sys/audioio.h> 42#include <dev/audio/audio_if.h> 43 44#include <dev/fdt/fdtvar.h> 45 46#include <arm/sunxi/sunxi_codec.h> 47 48#define TX_TRIG_LEVEL 0xf 49#define RX_TRIG_LEVEL 0x7 50#define DRQ_CLR_CNT 0x3 51 52#define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 53#define DAC_DPC_EN_DA 0x80000000 54#define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 55#define DAC_FIFOC_FS __BITS(31,29) 56#define DAC_FS_48KHZ 0 57#define DAC_FS_32KHZ 1 58#define DAC_FS_24KHZ 2 59#define DAC_FS_16KHZ 3 60#define DAC_FS_12KHZ 4 61#define DAC_FS_8KHZ 5 62#define DAC_FS_192KHZ 6 63#define DAC_FS_96KHZ 7 64#define DAC_FIFOC_FIFO_MODE __BITS(25,24) 65#define FIFO_MODE_24_31_8 0 66#define FIFO_MODE_16_31_16 0 67#define FIFO_MODE_16_15_0 1 68#define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 69#define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 70#define DAC_FIFOC_MONO_EN __BIT(6) 71#define DAC_FIFOC_TX_BITS __BIT(5) 72#define DAC_FIFOC_DRQ_EN __BIT(4) 73#define DAC_FIFOC_FIFO_FLUSH __BIT(0) 74#define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 75#define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 76#define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 77#define ADC_FIFOC_FS __BITS(31,29) 78#define ADC_FS_48KHZ 0 79#define ADC_FIFOC_EN_AD __BIT(28) 80#define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 81#define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 82#define ADC_FIFOC_MONO_EN __BIT(7) 83#define ADC_FIFOC_RX_BITS __BIT(6) 84#define ADC_FIFOC_DRQ_EN __BIT(4) 85#define ADC_FIFOC_FIFO_FLUSH __BIT(0) 86#define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 87#define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 88#define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 89#define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 90 91static const struct device_compatible_entry compat_data[] = { 92 A10_CODEC_COMPATDATA 93 A31_CODEC_COMPATDATA 94 H3_CODEC_COMPATDATA 95 V3S_CODEC_COMPATDATA 96 97 DEVICE_COMPAT_EOL 98}; 99 100#define CODEC_READ(sc, reg) \ 101 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 102#define CODEC_WRITE(sc, reg, val) \ 103 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 104 105static int 106sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 107 size_t align, struct sunxi_codec_dma *dma) 108{ 109 int error; 110 111 dma->dma_size = size; 112 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 113 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 114 if (error) 115 return error; 116 117 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 118 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 119 if (error) 120 goto free; 121 122 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 123 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 124 if (error) 125 goto unmap; 126 127 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 128 dma->dma_size, NULL, BUS_DMA_WAITOK); 129 if (error) 130 goto destroy; 131 132 return 0; 133 134destroy: 135 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 136unmap: 137 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 138free: 139 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 140 141 return error; 142} 143 144static void 145sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 146{ 147 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 148 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 149 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 150 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 151} 152 153static int 154sunxi_codec_transfer(struct sunxi_codec_chan *ch) 155{ 156 bus_dma_segment_t seg; 157 158 seg.ds_addr = ch->ch_cur_phys; 159 seg.ds_len = ch->ch_blksize; 160 ch->ch_req.dreq_segs = &seg; 161 ch->ch_req.dreq_nsegs = 1; 162 163 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 164} 165 166static int 167sunxi_codec_query_format(void *priv, audio_format_query_t *afp) 168{ 169 struct sunxi_codec_softc * const sc = priv; 170 171 return audio_query_format(&sc->sc_format, 1, afp); 172} 173 174static int 175sunxi_codec_set_format(void *priv, int setmode, 176 const audio_params_t *play, const audio_params_t *rec, 177 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 178{ 179 180 return 0; 181} 182 183static int 184sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 185{ 186 struct sunxi_codec_softc * const sc = priv; 187 188 return sc->sc_cfg->set_port(sc, mc); 189} 190 191static int 192sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 193{ 194 struct sunxi_codec_softc * const sc = priv; 195 196 return sc->sc_cfg->get_port(sc, mc); 197} 198 199static int 200sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 201{ 202 struct sunxi_codec_softc * const sc = priv; 203 204 return sc->sc_cfg->query_devinfo(sc, di); 205} 206 207static void * 208sunxi_codec_allocm(void *priv, int dir, size_t size) 209{ 210 struct sunxi_codec_softc * const sc = priv; 211 struct sunxi_codec_dma *dma; 212 int error; 213 214 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 215 216 error = sunxi_codec_allocdma(sc, size, 16, dma); 217 if (error) { 218 kmem_free(dma, sizeof(*dma)); 219 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 220 error); 221 return NULL; 222 } 223 224 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 225 226 return dma->dma_addr; 227} 228 229static void 230sunxi_codec_freem(void *priv, void *addr, size_t size) 231{ 232 struct sunxi_codec_softc * const sc = priv; 233 struct sunxi_codec_dma *dma; 234 235 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 236 if (dma->dma_addr == addr) { 237 sunxi_codec_freedma(sc, dma); 238 LIST_REMOVE(dma, dma_list); 239 kmem_free(dma, sizeof(*dma)); 240 break; 241 } 242} 243 244static int 245sunxi_codec_getdev(void *priv, struct audio_device *adev) 246{ 247 struct sunxi_codec_softc * const sc = priv; 248 249 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 250 snprintf(adev->version, sizeof(adev->version), "%s", 251 sc->sc_cfg->name); 252 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 253 254 return 0; 255} 256 257static int 258sunxi_codec_get_props(void *priv) 259{ 260 261 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE| 262 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 263} 264 265static int 266sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 267 void (*intr)(void *), void *intrarg, const audio_params_t *params) 268{ 269 struct sunxi_codec_softc * const sc = priv; 270 struct sunxi_codec_chan *ch = &sc->sc_pchan; 271 struct sunxi_codec_dma *dma; 272 bus_addr_t pstart; 273 bus_size_t psize; 274 uint32_t val; 275 int error; 276 277 pstart = 0; 278 psize = (uintptr_t)end - (uintptr_t)start; 279 280 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 281 if (dma->dma_addr == start) { 282 pstart = dma->dma_map->dm_segs[0].ds_addr; 283 break; 284 } 285 if (pstart == 0) { 286 device_printf(sc->sc_dev, "bad addr %p\n", start); 287 return EINVAL; 288 } 289 290 ch->ch_intr = intr; 291 ch->ch_intrarg = intrarg; 292 ch->ch_start_phys = ch->ch_cur_phys = pstart; 293 ch->ch_end_phys = pstart + psize; 294 ch->ch_blksize = blksize; 295 296 /* Flush DAC FIFO */ 297 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 298 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 299 300 /* Clear DAC FIFO status */ 301 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 302 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 303 304 /* Unmute output */ 305 if (sc->sc_cfg->mute) 306 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 307 308 /* Configure DAC FIFO */ 309 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 310 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 311 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 312 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 313 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 314 315 /* Enable DAC DRQ */ 316 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 317 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 318 319 /* Start DMA transfer */ 320 error = sunxi_codec_transfer(ch); 321 if (error != 0) { 322 aprint_error_dev(sc->sc_dev, 323 "failed to start DMA transfer: %d\n", error); 324 return error; 325 } 326 327 return 0; 328} 329 330static int 331sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 332 void (*intr)(void *), void *intrarg, const audio_params_t *params) 333{ 334 struct sunxi_codec_softc * const sc = priv; 335 struct sunxi_codec_chan *ch = &sc->sc_rchan; 336 struct sunxi_codec_dma *dma; 337 bus_addr_t pstart; 338 bus_size_t psize; 339 uint32_t val; 340 int error; 341 342 pstart = 0; 343 psize = (uintptr_t)end - (uintptr_t)start; 344 345 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 346 if (dma->dma_addr == start) { 347 pstart = dma->dma_map->dm_segs[0].ds_addr; 348 break; 349 } 350 if (pstart == 0) { 351 device_printf(sc->sc_dev, "bad addr %p\n", start); 352 return EINVAL; 353 } 354 355 ch->ch_intr = intr; 356 ch->ch_intrarg = intrarg; 357 ch->ch_start_phys = ch->ch_cur_phys = pstart; 358 ch->ch_end_phys = pstart + psize; 359 ch->ch_blksize = blksize; 360 361 /* Flush ADC FIFO */ 362 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 363 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 364 365 /* Clear ADC FIFO status */ 366 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 367 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 368 369 /* Unmute input */ 370 if (sc->sc_cfg->mute) 371 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 372 373 /* Configure ADC FIFO */ 374 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 375 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 376 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 377 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 378 379 /* Enable ADC DRQ */ 380 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 381 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 382 383 /* Start DMA transfer */ 384 error = sunxi_codec_transfer(ch); 385 if (error != 0) { 386 aprint_error_dev(sc->sc_dev, 387 "failed to start DMA transfer: %d\n", error); 388 return error; 389 } 390 391 return 0; 392} 393 394static int 395sunxi_codec_halt_output(void *priv) 396{ 397 struct sunxi_codec_softc * const sc = priv; 398 struct sunxi_codec_chan *ch = &sc->sc_pchan; 399 uint32_t val; 400 401 /* Disable DMA channel */ 402 fdtbus_dma_halt(ch->ch_dma); 403 404 /* flush fifo */ 405 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 406 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 407 while (val & DAC_FIFOC_FIFO_FLUSH) 408 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 409 410 /* Mute output */ 411 if (sc->sc_cfg->mute) 412 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 413 414 /* Disable DAC DRQ */ 415 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 416 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 417 418 ch->ch_intr = NULL; 419 ch->ch_intrarg = NULL; 420 421 return 0; 422} 423 424static int 425sunxi_codec_halt_input(void *priv) 426{ 427 struct sunxi_codec_softc * const sc = priv; 428 struct sunxi_codec_chan *ch = &sc->sc_rchan; 429 uint32_t val; 430 431 /* Mute output */ 432 if (sc->sc_cfg->mute) 433 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 434 435 /* flush fifo */ 436 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 437 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 438 while (val & ADC_FIFOC_FIFO_FLUSH) 439 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 440 441 /* Disable DMA channel */ 442 fdtbus_dma_halt(ch->ch_dma); 443 444 /* Disable ADC DRQ */ 445 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 446 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 447 448 return 0; 449} 450 451static void 452sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 453{ 454 struct sunxi_codec_softc * const sc = priv; 455 456 *intr = &sc->sc_intr_lock; 457 *thread = &sc->sc_lock; 458} 459 460static const struct audio_hw_if sunxi_codec_hw_if = { 461 .query_format = sunxi_codec_query_format, 462 .set_format = sunxi_codec_set_format, 463 .allocm = sunxi_codec_allocm, 464 .freem = sunxi_codec_freem, 465 .getdev = sunxi_codec_getdev, 466 .set_port = sunxi_codec_set_port, 467 .get_port = sunxi_codec_get_port, 468 .query_devinfo = sunxi_codec_query_devinfo, 469 .get_props = sunxi_codec_get_props, 470 .trigger_output = sunxi_codec_trigger_output, 471 .trigger_input = sunxi_codec_trigger_input, 472 .halt_output = sunxi_codec_halt_output, 473 .halt_input = sunxi_codec_halt_input, 474 .get_locks = sunxi_codec_get_locks, 475}; 476 477static void 478sunxi_codec_dmaintr(void *priv) 479{ 480 struct sunxi_codec_chan * const ch = priv; 481 struct sunxi_codec_softc * const sc = ch->ch_sc; 482 483 mutex_enter(&sc->sc_intr_lock); 484 ch->ch_cur_phys += ch->ch_blksize; 485 if (ch->ch_cur_phys >= ch->ch_end_phys) 486 ch->ch_cur_phys = ch->ch_start_phys; 487 488 if (ch->ch_intr) { 489 ch->ch_intr(ch->ch_intrarg); 490 sunxi_codec_transfer(ch); 491 } 492 mutex_exit(&sc->sc_intr_lock); 493} 494 495static int 496sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 497 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 498{ 499 ch->ch_sc = sc; 500 ch->ch_mode = mode; 501 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 502 if (ch->ch_dma == NULL) { 503 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 504 return ENXIO; 505 } 506 507 if (mode == AUMODE_PLAY) { 508 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 509 ch->ch_req.dreq_dev_phys = 510 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 511 } else { 512 ch->ch_req.dreq_dir = FDT_DMA_READ; 513 ch->ch_req.dreq_dev_phys = 514 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 515 } 516 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 517 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 518 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 519 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 520 521 return 0; 522} 523 524static int 525sunxi_codec_clock_init(int phandle) 526{ 527 struct fdtbus_reset *rst; 528 struct clk *clk; 529 int error; 530 531 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 532 clk = fdtbus_clock_get(phandle, "codec"); 533 if (clk == NULL) { 534 aprint_error(": couldn't find codec clock\n"); 535 return ENXIO; 536 } 537 error = clk_set_rate(clk, 24576000); 538 if (error != 0) { 539 aprint_error(": couldn't set codec clock rate: %d\n", error); 540 return error; 541 } 542 error = clk_enable(clk); 543 if (error != 0) { 544 aprint_error(": couldn't enable codec clock: %d\n", error); 545 return error; 546 } 547 548 /* Enable APB clock */ 549 clk = fdtbus_clock_get(phandle, "apb"); 550 if (clk == NULL) { 551 aprint_error(": couldn't find apb clock\n"); 552 return ENXIO; 553 } 554 error = clk_enable(clk); 555 if (error != 0) { 556 aprint_error(": couldn't enable apb clock: %d\n", error); 557 return error; 558 } 559 560 /* De-assert reset */ 561 rst = fdtbus_reset_get_index(phandle, 0); 562 if (rst != NULL) { 563 error = fdtbus_reset_deassert(rst); 564 if (error != 0) { 565 aprint_error(": couldn't de-assert reset: %d\n", error); 566 return error; 567 } 568 } 569 570 return 0; 571} 572 573static int 574sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 575{ 576 struct fdt_attach_args * const faa = aux; 577 578 return of_compatible_match(faa->faa_phandle, compat_data); 579} 580 581static void 582sunxi_codec_attach(device_t parent, device_t self, void *aux) 583{ 584 struct sunxi_codec_softc * const sc = device_private(self); 585 struct fdt_attach_args * const faa = aux; 586 const int phandle = faa->faa_phandle; 587 bus_addr_t addr; 588 bus_size_t size; 589 uint32_t val; 590 591 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 592 aprint_error(": couldn't get registers\n"); 593 return; 594 } 595 596 if (sunxi_codec_clock_init(phandle) != 0) 597 return; 598 599 sc->sc_dev = self; 600 sc->sc_phandle = phandle; 601 sc->sc_baseaddr = addr; 602 sc->sc_bst = faa->faa_bst; 603 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 604 aprint_error(": couldn't map registers\n"); 605 return; 606 } 607 sc->sc_dmat = faa->faa_dmat; 608 LIST_INIT(&sc->sc_dmalist); 609 sc->sc_cfg = of_compatible_lookup(phandle, compat_data)->data; 610 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 611 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 612 613 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 614 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 615 aprint_error(": couldn't setup channels\n"); 616 return; 617 } 618 619 /* Optional PA mute GPIO */ 620 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 621 622 aprint_naive("\n"); 623 aprint_normal(": %s\n", sc->sc_cfg->name); 624 625 /* Enable DAC */ 626 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 627 val |= DAC_DPC_EN_DA; 628 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 629 630 /* Initialize codec */ 631 if (sc->sc_cfg->init(sc) != 0) { 632 aprint_error_dev(self, "couldn't initialize codec\n"); 633 return; 634 } 635 636 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 637 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 638 sc->sc_format.validbits = 16; 639 sc->sc_format.precision = 16; 640 sc->sc_format.channels = 2; 641 sc->sc_format.channel_mask = AUFMT_STEREO; 642 sc->sc_format.frequency_type = 1; 643 sc->sc_format.frequency[0] = 48000; 644 645 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 646} 647 648CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 649 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 650 651#ifdef DDB 652void sunxicodec_dump(void); 653 654void 655sunxicodec_dump(void) 656{ 657 struct sunxi_codec_softc *sc; 658 device_t dev; 659 660 dev = device_find_by_driver_unit("sunxicodec", 0); 661 if (dev == NULL) 662 return; 663 sc = device_private(dev); 664 665 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 666 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 667 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 668 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 669 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 670 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 671 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 672} 673#endif 674