1/* $NetBSD: sun9i_a80_usbphy.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: sun9i_a80_usbphy.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/time.h>
39
40#include <dev/fdt/fdtvar.h>
41
42/* PMU registers */
43#define	PMU_CFG			0x00
44#define	 EHCI_HS_FORCE		__BIT(20)
45#define	 HSIC_CONNECT_DET	__BIT(17)
46#define	 HSIC_CONNECT_INT	__BIT(16)
47#define	 AHB_INCR16		__BIT(11)
48#define	 AHB_INCR8		__BIT(10)
49#define	 AHB_INCR4		__BIT(9)
50#define	 AHB_INCRX_ALIGN	__BIT(8)
51#define	 HSIC			__BIT(1)
52#define	 ULPI_BYPASS		__BIT(0)
53
54static int sun9i_usbphy_match(device_t, cfdata_t, void *);
55static void sun9i_usbphy_attach(device_t, device_t, void *);
56
57static const struct device_compatible_entry compat_data[] = {
58	{ .compat = "allwinner,sun9i-a80-usb-phy" },
59	DEVICE_COMPAT_EOL
60};
61
62struct sun9i_usbphy_softc {
63	device_t		sc_dev;
64	bus_space_tag_t		sc_bst;
65	bus_space_handle_t	sc_bsh;
66
67	struct clk		*sc_clk_phy;
68	struct clk		*sc_clk_hsic;
69	struct fdtbus_reset	*sc_rst;
70
71	struct fdtbus_regulator	*sc_supply;
72};
73
74#define	PHY_READ(sc, reg)				\
75	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
76#define	PHY_WRITE(sc, reg, val)				\
77	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
78
79CFATTACH_DECL_NEW(sunxi_a80_usbphy, sizeof(struct sun9i_usbphy_softc),
80	sun9i_usbphy_match, sun9i_usbphy_attach, NULL, NULL);
81
82static void *
83sun9i_usbphy_acquire(device_t dev, const void *data, size_t len)
84{
85	struct sun9i_usbphy_softc * const sc = device_private(dev);
86
87	return sc;
88}
89
90static void
91sun9i_usbphy_release(device_t dev, void *priv)
92{
93}
94
95static int
96sun9i_usbphy_enable(device_t dev, void *priv, bool enable)
97{
98	struct sun9i_usbphy_softc * const sc = device_private(dev);
99	uint32_t passby_mask;
100	uint32_t val;
101	int error;
102
103	passby_mask = ULPI_BYPASS|AHB_INCR16|AHB_INCR8|AHB_INCR4|AHB_INCRX_ALIGN;
104	if (sc->sc_clk_hsic != NULL)
105		passby_mask |= HSIC|EHCI_HS_FORCE|HSIC_CONNECT_DET|HSIC_CONNECT_INT;
106
107	/* Enable/disable passby */
108	if (enable) {
109		error = clk_enable(sc->sc_clk_phy);
110		if (error != 0)
111			return error;
112
113		if (sc->sc_clk_hsic != NULL) {
114			error = clk_enable(sc->sc_clk_hsic);
115			if (error != 0)
116				return error;
117		}
118
119		error = fdtbus_reset_deassert(sc->sc_rst);
120		if (error != 0)
121			return error;
122
123		val = PHY_READ(sc, PMU_CFG);
124		val |= passby_mask;
125		PHY_WRITE(sc, PMU_CFG, val);
126	} else {
127		val = PHY_READ(sc, PMU_CFG);
128		val &= ~passby_mask;
129		PHY_WRITE(sc, PMU_CFG, val);
130
131		error = fdtbus_reset_assert(sc->sc_rst);
132		if (error != 0)
133			return error;
134
135		if (sc->sc_clk_hsic != NULL) {
136			error = clk_disable(sc->sc_clk_hsic);
137			if (error != 0)
138				return error;
139		}
140
141		error = clk_disable(sc->sc_clk_phy);
142		if (error != 0)
143			return error;
144	}
145
146	return 0;
147}
148
149const struct fdtbus_phy_controller_func sun9i_usbphy_funcs = {
150	.acquire = sun9i_usbphy_acquire,
151	.release = sun9i_usbphy_release,
152	.enable = sun9i_usbphy_enable,
153};
154
155static int
156sun9i_usbphy_match(device_t parent, cfdata_t cf, void *aux)
157{
158	struct fdt_attach_args * const faa = aux;
159
160	return of_compatible_match(faa->faa_phandle, compat_data);
161}
162
163static void
164sun9i_usbphy_attach(device_t parent, device_t self, void *aux)
165{
166	struct sun9i_usbphy_softc * const sc = device_private(self);
167	struct fdt_attach_args * const faa = aux;
168	const int phandle = faa->faa_phandle;
169	const char *phy_type;
170	bus_addr_t addr;
171	bus_size_t size;
172
173	sc->sc_dev = self;
174	sc->sc_bst = faa->faa_bst;
175
176	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
177		aprint_error(": couldn't get registers\n");
178		return;
179	}
180	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
181		aprint_error(": couldn't map registers\n");
182		return;
183	}
184
185	phy_type = fdtbus_get_string(phandle, "phy_type");
186	if (phy_type && strcmp(phy_type, "hsic") == 0) {
187		sc->sc_clk_phy = fdtbus_clock_get(phandle, "hsic_480M");
188		sc->sc_clk_hsic = fdtbus_clock_get(phandle, "hsic_12M");
189		sc->sc_rst = fdtbus_reset_get(phandle, "hsic");
190
191		if (sc->sc_clk_phy == NULL || sc->sc_clk_hsic == NULL || sc->sc_rst == NULL) {
192			aprint_error(": couldn't get hsic resources\n");
193			return;
194		}
195	} else {
196		sc->sc_clk_phy = fdtbus_clock_get(phandle, "phy");
197		sc->sc_rst = fdtbus_reset_get(phandle, "phy");
198		if (sc->sc_clk_phy == NULL || sc->sc_rst == NULL) {
199			aprint_error(": couldn't get phy resources\n");
200			return;
201		}
202	}
203
204	aprint_naive("\n");
205	aprint_normal(": USB PHY\n");
206
207	sc->sc_supply = fdtbus_regulator_acquire(phandle, "phy-supply");
208	if (sc->sc_supply != NULL) {
209		if (fdtbus_regulator_enable(sc->sc_supply) != 0)
210			aprint_error_dev(self, "WARNING: couldn't enable power supply\n");
211	}
212
213	fdtbus_register_phy_controller(self, phandle, &sun9i_usbphy_funcs);
214}
215