sun8i_a23_apbclk.c revision 1.1 
1/* $NetBSD: sun8i_a23_apbclk.c,v 1.1 2019/05/27 21:12:54 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: sun8i_a23_apbclk.c,v 1.1 2019/05/27 21:12:54 jmcneill Exp $");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/device.h>
35#include <sys/kmem.h>
36#include <sys/bus.h>
37
38#include <dev/clk/clk_backend.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	APB0_DIV	__BITS(1,0)
43
44static int	sun8i_a23_apbclk_match(device_t, cfdata_t, void *);
45static void	sun8i_a23_apbclk_attach(device_t, device_t, void *);
46
47static struct clk *sun8i_a23_apbclk_decode(device_t, int, const void *, size_t);
48
49static const struct fdtbus_clock_controller_func sun8i_a23_apbclk_fdt_funcs = {
50	.decode = sun8i_a23_apbclk_decode
51};
52
53static struct clk *sun8i_a23_apbclk_get(void *, const char *);
54static void	sun8i_a23_apbclk_put(void *, struct clk *);
55static int	sun8i_a23_apbclk_set_rate(void *, struct clk *, u_int);
56static u_int	sun8i_a23_apbclk_get_rate(void *, struct clk *);
57static struct clk *sun8i_a23_apbclk_get_parent(void *, struct clk *);
58
59static const struct clk_funcs sun8i_a23_apbclk_clk_funcs = {
60	.get = sun8i_a23_apbclk_get,
61	.put = sun8i_a23_apbclk_put,
62	.set_rate = sun8i_a23_apbclk_set_rate,
63	.get_rate = sun8i_a23_apbclk_get_rate,
64	.get_parent = sun8i_a23_apbclk_get_parent,
65};
66
67struct sun8i_a23_apbclk_softc {
68	device_t		sc_dev;
69	int			sc_phandle;
70	bus_space_tag_t		sc_bst;
71	bus_space_handle_t	sc_bsh;
72
73	struct clk_domain	sc_clkdom;
74	struct clk		sc_clk;
75	struct clk		*sc_parent;
76};
77
78#define	RD4(sc, reg)			\
79	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
80#define	WR4(sc, reg, val)		\
81	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82
83CFATTACH_DECL_NEW(sunxi_a23_apbclk, sizeof(struct sun8i_a23_apbclk_softc),
84    sun8i_a23_apbclk_match, sun8i_a23_apbclk_attach, NULL, NULL);
85
86static int
87sun8i_a23_apbclk_match(device_t parent, cfdata_t cf, void *aux)
88{
89	const char * const compatible[] = { "allwinner,sun8i-a23-apb0-clk", NULL };
90	const struct fdt_attach_args *faa = aux;
91
92	return of_match_compatible(faa->faa_phandle, compatible);
93}
94
95static void
96sun8i_a23_apbclk_attach(device_t parent, device_t self, void *aux)
97{
98	struct sun8i_a23_apbclk_softc * const sc = device_private(self);
99	const struct fdt_attach_args *faa = aux;
100	const int phandle = faa->faa_phandle;
101	bus_addr_t addr;
102	bus_size_t size;
103
104	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
105		aprint_error(": couldn't get registers\n");
106		return;
107	}
108
109	sc->sc_dev = self;
110	sc->sc_phandle = phandle;
111	sc->sc_bst = faa->faa_bst;
112	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
113		aprint_error(": couldn't map registers\n");
114		return;
115	}
116	sc->sc_parent = fdtbus_clock_get_index(phandle, 0);
117
118	sc->sc_clkdom.funcs = &sun8i_a23_apbclk_clk_funcs;
119	sc->sc_clkdom.priv = sc;
120
121	sc->sc_clk.domain = &sc->sc_clkdom;
122	sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
123
124	aprint_naive("\n");
125	aprint_normal(": A23 APB0 clock\n");
126
127	fdtbus_register_clock_controller(self, phandle, &sun8i_a23_apbclk_fdt_funcs);
128}
129
130static struct clk *
131sun8i_a23_apbclk_decode(device_t dev, int cc_phandle, const void *data,
132		     size_t len)
133{
134	struct sun8i_a23_apbclk_softc * const sc = device_private(dev);
135
136	if (len != 0)
137		return NULL;
138
139	return &sc->sc_clk;
140}
141
142static struct clk *
143sun8i_a23_apbclk_get(void *priv, const char *name)
144{
145	struct sun8i_a23_apbclk_softc * const sc = priv;
146
147	if (strcmp(name, sc->sc_clk.name) != 0)
148		return NULL;
149
150	return &sc->sc_clk;
151}
152
153static void
154sun8i_a23_apbclk_put(void *priv, struct clk *clk)
155{
156}
157
158static int
159sun8i_a23_apbclk_set_rate(void *priv, struct clk *clk, u_int rate)
160{
161	return ENXIO;
162}
163
164static u_int
165sun8i_a23_apbclk_get_rate(void *priv, struct clk *clk)
166{
167	struct sun8i_a23_apbclk_softc * const sc = priv;
168	struct clk *clk_parent = clk_get_parent(clk);
169
170	const uint32_t val = RD4(sc, 0);
171	const u_int div = __SHIFTOUT(val, APB0_DIV);
172
173	return clk_get_rate(clk_parent) / (div + 1);
174}
175
176static struct clk *
177sun8i_a23_apbclk_get_parent(void *priv, struct clk *clk)
178{
179	struct sun8i_a23_apbclk_softc * const sc = priv;
180
181	return sc->sc_parent;
182}
183