1/*	$NetBSD: sun6i_spireg.h,v 1.1 2018/02/06 12:45:39 jakllsch Exp $	*/
2
3/*
4 * Copyright (c) 2018 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _SUNXI_SUN6I_SPIREG_H_
30#define _SUNXI_SUN6I_SPIREG_H_
31
32#include <sys/cdefs.h>
33
34#define SPI_GCR		0x004
35#define SPI_GCR_SRST		__BIT(31)
36#define SPI_GCR_TP_EN		__BIT(7)
37#define SPI_GCR_MODE		__BIT(1)
38#define SPI_GCR_MODE_SLAVE	(0)
39#define SPI_GCR_MODE_MASTER	(1)
40#define SPI_GCR_EN		__BIT(0)
41
42#define SPI_TCR		0x008
43#define SPI_TCR_XCH		__BIT(31)
44#define SPI_TCR_SDDM		__BIT(14)
45#define SPI_TCR_SDM		__BIT(13)
46#define SPI_TCR_FBS		__BIT(12)
47#define SPI_TCR_SDC		__BIT(11)
48#define SPI_TCR_RPSM		__BIT(10)
49#define SPI_TCR_DDB		__BIT(9)
50#define SPI_TCR_DHB		__BIT(8)
51#define SPI_TCR_SS_LEVEL	__BIT(7)
52#define SPI_TCR_SS_OWNER	__BIT(6)
53#define SPI_TCR_SS_SEL		__BITS(5,4)
54#define SPI_TCR_SSCTL		__BIT(3)
55#define SPI_TCR_SPOL		__BIT(2)
56#define SPI_TCR_CPOL		__BIT(1)
57#define SPI_TCR_CPHA		__BIT(0)
58
59#define SPI_IER		0x010
60#define SPI_IER_SS_INT_EN	__BIT(13)
61#define SPI_IER_TC_INT_EN	__BIT(12)
62#define SPI_IER_TF_UDR_INT_EN	__BIT(11)
63#define SPI_IER_TF_OVF_INT_EN	__BIT(10)
64#define SPI_IER_RF_UDR_INT_EN	__BIT(9)
65#define SPI_IER_RF_OVF_INT_EN	__BIT(8)
66#define SPI_IER_TF_FUL_INT_EN	__BIT(6)
67#define SPI_IER_TX_EMP_INT_EN	__BIT(5)
68#define SPI_IER_TX_ERQ_INT_EN	__BIT(4)
69#define SPI_IER_RF_FUL_INT_EN	__BIT(2)
70#define SPI_IER_RX_EMP_INT_EN	__BIT(1)
71#define SPI_IER_RF_RDY_INT_EN	__BIT(0)
72
73#define SPI_INT_STA	0x014
74#define SPI_ISR_SSI		__BIT(13)
75#define SPI_ISR_TC		__BIT(12)
76#define SPI_ISR_TF_UDF		__BIT(11)
77#define SPI_ISR_TF_OVF		__BIT(10)
78#define SPI_ISR_RX_UDF		__BIT(9)
79#define SPI_ISR_RX_OVF		__BIT(8)
80#define SPI_ISR_TX_FULL		__BIT(6)
81#define SPI_ISR_TX_EMP		__BIT(5)
82#define SPI_ISR_TX_READY	__BIT(4)
83#define SPI_ISR_RX_FULL		__BIT(2)
84#define SPI_ISR_RX_EMP		__BIT(1)
85#define SPI_ISR_RX_RDY		__BIT(0)
86
87#define SPI_FCR		0x018
88#define SPI_FCR_TX_FIFO_RST	__BIT(31)
89#define SPI_FCR_TF_TEST		__BIT(30)
90#define SPI_FCR_TF_DRQ_EN	__BIT(24)
91#define SPI_FCR_TX_TRIG_LEVEL	__BITS(23,16)
92#define SPI_FCR_RF_RST		__BIT(15)
93#define SPI_FCR_RF_TEST		__BIT(14)
94#define SPI_FCR_RX_DMA_MODE	__BIT(9)
95#define SPI_FCR_RF_DRQ_EN	__BIT(8)
96#define SPI_FCR_RX_TRIG_LEVEL	__BITS(7,0)
97
98#define SPI_FSR		0x01c
99#define SPI_FSR_TB_WR		__BIT(31)
100#define SPI_FSR_TB_CNT		__BITS(30,28)
101#define SPI_FSR_TF_CNT		__BITS(23,16)
102#define SPI_FSR_RB_WR		__BIT(15)
103#define SPI_FSR_RB_CNT		__BITS(14,12)
104#define SPI_FSR_RF_CNT		__BITS(7,0)
105
106#define SPI_WCR		0x020
107#define SPI_WCR_SWC		__BITS(19,16)
108#define SPI_WCR_WCC		__BITS(15,0)
109
110#define SPI_CCTL	0x024
111#define SPI_CCTL_DRS		__BIT(12)
112#define SPI_CCTL_CDR1		__BITS(11,8)
113#define SPI_CCTL_CDR2		__BITS(7,0)
114
115#define SPI_BC		0x030
116#define SPI_BC_MBC		__BITS(23,0)
117
118#define SPI_TC		0x034
119#define SPI_TC_MWTC		__BITS(23,0)
120
121#define SPI_BCC		0x038
122#define SPI_BCC_DRM		__BIT(28)
123#define SPI_BCC_DBC		__BITS(27,24)
124#define SPI_BCC_STC		__BITS(23,0)
125
126#define SPI_NDMA_CTL	0x088
127#define SPI_NDMA_CTL_NDMA_MODE_CTL	__BITS(7,0)
128
129#define SPI_TXD		0x200
130#define SPI_TXD_TDATA_4		__BITS(31,0)
131
132#define SPI_RXD		0x300
133#define SPI_RXD_RDATA_4		__BITS(31,0)
134
135#endif /* _SUNXI_SUN6I_SPIREG_H_ */
136