sun50i_a64_acodec.c revision 1.4
1/* $NetBSD: sun50i_a64_acodec.c,v 1.4 2018/05/11 23:05:41 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: sun50i_a64_acodec.c,v 1.4 2018/05/11 23:05:41 jmcneill Exp $"); 31 32#include <sys/param.h> 33#include <sys/bus.h> 34#include <sys/cpu.h> 35#include <sys/device.h> 36#include <sys/kmem.h> 37#include <sys/bitops.h> 38 39#include <dev/audio_dai.h> 40 41#include <dev/fdt/fdtvar.h> 42 43#define A64_PR_CFG 0x00 44#define A64_AC_PR_RST __BIT(28) 45#define A64_AC_PR_RW __BIT(24) 46#define A64_AC_PR_ADDR __BITS(20,16) 47#define A64_ACDA_PR_WDAT __BITS(15,8) 48#define A64_ACDA_PR_RDAT __BITS(7,0) 49 50#define A64_HP_CTRL 0x00 51#define A64_HPPA_EN __BIT(6) 52#define A64_HPVOL __BITS(5,0) 53#define A64_OL_MIX_CTRL 0x01 54#define A64_LMIXMUTE_LDAC __BIT(1) 55#define A64_OR_MIX_CTRL 0x02 56#define A64_RMIXMUTE_RDAC __BIT(1) 57#define A64_LINEOUT_CTRL0 0x05 58#define A64_LINEOUT_LEFT_EN __BIT(7) 59#define A64_LINEOUT_RIGHT_EN __BIT(6) 60#define A64_LINEOUT_CTRL1 0x06 61#define A64_LINEOUT_VOL __BITS(4,0) 62#define A64_MIC1_CTRL 0x07 63#define A64_MIC1G __BITS(6,4) 64#define A64_MIC1AMPEN __BIT(3) 65#define A64_MIC1BOOST __BITS(2,0) 66#define A64_MIC2_CTRL 0x08 67#define A64_MIC2_SEL __BIT(7) 68#define A64_MIC2G __BITS(6,4) 69#define A64_MIC2AMPEN __BIT(3) 70#define A64_MIC2BOOST __BITS(2,0) 71#define A64_LINEIN_CTRL 0x09 72#define A64_LINEING __BITS(6,4) 73#define A64_MIX_DAC_CTRL 0x0a 74#define A64_DACAREN __BIT(7) 75#define A64_DACALEN __BIT(6) 76#define A64_RMIXEN __BIT(5) 77#define A64_LMIXEN __BIT(4) 78#define A64_RHPPAMUTE __BIT(3) 79#define A64_LHPPAMUTE __BIT(2) 80#define A64_RHPIS __BIT(1) 81#define A64_LHPIS __BIT(0) 82#define A64_L_ADCMIX_SRC 0x0b 83#define A64_R_ADCMIX_SRC 0x0c 84#define A64_ADCMIX_SRC_MIC1 __BIT(6) 85#define A64_ADCMIX_SRC_MIC2 __BIT(5) 86#define A64_ADCMIX_SRC_LINEIN __BIT(2) 87#define A64_ADCMIX_SRC_OMIXER __BIT(0) 88#define A64_ADC_CTRL 0x0d 89#define A64_ADCREN __BIT(7) 90#define A64_ADCLEN __BIT(6) 91#define A64_ADCG __BITS(2,0) 92#define A64_JACK_MIC_CTRL 0x1d 93#define A64_JACKDETEN __BIT(7) 94#define A64_INNERRESEN __BIT(6) 95#define A64_AUTOPLEN __BIT(1) 96 97struct a64_acodec_softc { 98 device_t sc_dev; 99 bus_space_tag_t sc_bst; 100 bus_space_handle_t sc_bsh; 101 int sc_phandle; 102 103 struct audio_dai_device sc_dai; 104}; 105 106enum a64_acodec_mixer_ctrl { 107 A64_CODEC_OUTPUT_CLASS, 108 A64_CODEC_INPUT_CLASS, 109 A64_CODEC_RECORD_CLASS, 110 111 A64_CODEC_OUTPUT_MASTER_VOLUME, 112 A64_CODEC_OUTPUT_HP_VOLUME, 113 A64_CODEC_INPUT_DAC_VOLUME, 114 A64_CODEC_INPUT_LINEIN_VOLUME, 115 A64_CODEC_INPUT_MIC1_VOLUME, 116 A64_CODEC_INPUT_MIC2_VOLUME, 117 A64_CODEC_RECORD_AGC_VOLUME, 118 A64_CODEC_RECORD_SOURCE, 119 120 A64_CODEC_MIXER_CTRL_LAST 121}; 122 123static const struct a64_acodec_mixer { 124 const char * name; 125 enum a64_acodec_mixer_ctrl mixer_class; 126 u_int reg; 127 u_int mask; 128} a64_acodec_mixers[A64_CODEC_MIXER_CTRL_LAST] = { 129 [A64_CODEC_OUTPUT_MASTER_VOLUME] = { AudioNmaster, 130 A64_CODEC_OUTPUT_CLASS, A64_LINEOUT_CTRL1, A64_LINEOUT_VOL }, 131 [A64_CODEC_OUTPUT_HP_VOLUME] = { AudioNheadphone, 132 A64_CODEC_OUTPUT_CLASS, A64_HP_CTRL, A64_HPVOL }, 133 [A64_CODEC_INPUT_DAC_VOLUME] = { AudioNdac, 134 A64_CODEC_INPUT_CLASS, A64_LINEOUT_CTRL1, A64_LINEOUT_VOL }, 135 [A64_CODEC_INPUT_LINEIN_VOLUME] = { AudioNline, 136 A64_CODEC_INPUT_CLASS, A64_LINEIN_CTRL, A64_LINEING }, 137 [A64_CODEC_INPUT_MIC1_VOLUME] = { "mic1", 138 A64_CODEC_INPUT_CLASS, A64_MIC1_CTRL, A64_MIC1G }, 139 [A64_CODEC_INPUT_MIC2_VOLUME] = { "mic2", 140 A64_CODEC_INPUT_CLASS, A64_MIC2_CTRL, A64_MIC2G }, 141 [A64_CODEC_RECORD_AGC_VOLUME] = { AudioNagc, 142 A64_CODEC_RECORD_CLASS, A64_ADC_CTRL, A64_ADCG }, 143}; 144 145#define RD4(sc, reg) \ 146 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 147#define WR4(sc, reg, val) \ 148 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 149 150static u_int 151a64_acodec_pr_read(struct a64_acodec_softc *sc, u_int addr) 152{ 153 uint32_t val; 154 155 /* Read current value */ 156 val = RD4(sc, A64_PR_CFG); 157 158 /* De-assert reset */ 159 val |= A64_AC_PR_RST; 160 WR4(sc, A64_PR_CFG, val); 161 162 /* Read mode */ 163 val &= ~A64_AC_PR_RW; 164 WR4(sc, A64_PR_CFG, val); 165 166 /* Set address */ 167 val &= ~A64_AC_PR_ADDR; 168 val |= __SHIFTIN(addr, A64_AC_PR_ADDR); 169 WR4(sc, A64_PR_CFG, val); 170 171 /* Read data */ 172 return __SHIFTOUT(RD4(sc, A64_PR_CFG), A64_ACDA_PR_RDAT); 173} 174 175static void 176a64_acodec_pr_write(struct a64_acodec_softc *sc, u_int addr, u_int data) 177{ 178 uint32_t val; 179 180 /* Read current value */ 181 val = RD4(sc, A64_PR_CFG); 182 183 /* De-assert reset */ 184 val |= A64_AC_PR_RST; 185 WR4(sc, A64_PR_CFG, val); 186 187 /* Set address */ 188 val &= ~A64_AC_PR_ADDR; 189 val |= __SHIFTIN(addr, A64_AC_PR_ADDR); 190 WR4(sc, A64_PR_CFG, val); 191 192 /* Write data */ 193 val &= ~A64_ACDA_PR_WDAT; 194 val |= __SHIFTIN(data, A64_ACDA_PR_WDAT); 195 WR4(sc, A64_PR_CFG, val); 196 197 /* Write mode */ 198 val |= A64_AC_PR_RW; 199 WR4(sc, A64_PR_CFG, val); 200 201 /* Clear write mode */ 202 val &= ~A64_AC_PR_RW; 203 WR4(sc, A64_PR_CFG, val); 204} 205 206static void 207a64_acodec_pr_set_clear(struct a64_acodec_softc *sc, u_int addr, u_int set, u_int clr) 208{ 209 u_int old, new; 210 211 old = a64_acodec_pr_read(sc, addr); 212 new = set | (old & ~clr); 213 a64_acodec_pr_write(sc, addr, new); 214} 215 216static int 217a64_acodec_trigger_output(void *priv, void *start, void *end, int blksize, 218 void (*intr)(void *), void *intrarg, const audio_params_t *params) 219{ 220 struct a64_acodec_softc * const sc = priv; 221 222 /* Enable DAC analog l/r channels, HP PA, and output mixer */ 223 a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL, 224 A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN | 225 A64_RHPPAMUTE | A64_LHPPAMUTE, 0); 226 /* Unmute DAC l/r channels to output mixer */ 227 a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL, 228 A64_LMIXMUTE_LDAC, 0); 229 a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL, 230 A64_RMIXMUTE_RDAC, 0); 231 232 return 0; 233} 234 235static int 236a64_acodec_trigger_input(void *priv, void *start, void *end, int blksize, 237 void (*intr)(void *), void *intrarg, const audio_params_t *params) 238{ 239 struct a64_acodec_softc * const sc = priv; 240 241 /* Enable ADC analog l/r channels */ 242 a64_acodec_pr_set_clear(sc, A64_ADC_CTRL, 243 A64_ADCREN | A64_ADCLEN, 0); 244 245 return 0; 246} 247 248static int 249a64_acodec_halt_output(void *priv) 250{ 251 struct a64_acodec_softc * const sc = priv; 252 253 /* Mute DAC l/r channels to output mixer */ 254 a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL, 255 0, A64_LMIXMUTE_LDAC); 256 a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL, 257 0, A64_RMIXMUTE_RDAC); 258 /* Disable DAC analog l/r channels, HP PA, and output mixer */ 259 a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL, 260 0, A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN | 261 A64_RHPPAMUTE | A64_LHPPAMUTE); 262 263 return 0; 264} 265 266static int 267a64_acodec_halt_input(void *priv) 268{ 269 struct a64_acodec_softc * const sc = priv; 270 271 /* Disable ADC analog l/r channels */ 272 a64_acodec_pr_set_clear(sc, A64_ADC_CTRL, 273 0, A64_ADCREN | A64_ADCLEN); 274 275 return 0; 276} 277 278static int 279a64_acodec_set_port(void *priv, mixer_ctrl_t *mc) 280{ 281 struct a64_acodec_softc * const sc = priv; 282 const struct a64_acodec_mixer *mix; 283 u_int val, shift; 284 int nvol; 285 286 switch (mc->dev) { 287 case A64_CODEC_OUTPUT_MASTER_VOLUME: 288 case A64_CODEC_OUTPUT_HP_VOLUME: 289 case A64_CODEC_INPUT_DAC_VOLUME: 290 case A64_CODEC_INPUT_LINEIN_VOLUME: 291 case A64_CODEC_INPUT_MIC1_VOLUME: 292 case A64_CODEC_INPUT_MIC2_VOLUME: 293 case A64_CODEC_RECORD_AGC_VOLUME: 294 mix = &a64_acodec_mixers[mc->dev]; 295 val = a64_acodec_pr_read(sc, mix->reg); 296 shift = 8 - fls32(__SHIFTOUT_MASK(mix->mask)); 297 nvol = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> shift; 298 val &= ~mix->mask; 299 val |= __SHIFTIN(nvol, mix->mask); 300 a64_acodec_pr_write(sc, mix->reg, val); 301 return 0; 302 303 case A64_CODEC_RECORD_SOURCE: 304 a64_acodec_pr_write(sc, A64_L_ADCMIX_SRC, mc->un.mask); 305 a64_acodec_pr_write(sc, A64_R_ADCMIX_SRC, mc->un.mask); 306 return 0; 307 } 308 309 return ENXIO; 310} 311 312static int 313a64_acodec_get_port(void *priv, mixer_ctrl_t *mc) 314{ 315 struct a64_acodec_softc * const sc = priv; 316 const struct a64_acodec_mixer *mix; 317 u_int val, shift; 318 int nvol; 319 320 switch (mc->dev) { 321 case A64_CODEC_OUTPUT_MASTER_VOLUME: 322 case A64_CODEC_OUTPUT_HP_VOLUME: 323 case A64_CODEC_INPUT_DAC_VOLUME: 324 case A64_CODEC_INPUT_LINEIN_VOLUME: 325 case A64_CODEC_INPUT_MIC1_VOLUME: 326 case A64_CODEC_INPUT_MIC2_VOLUME: 327 case A64_CODEC_RECORD_AGC_VOLUME: 328 mix = &a64_acodec_mixers[mc->dev]; 329 val = a64_acodec_pr_read(sc, mix->reg); 330 shift = 8 - fls32(__SHIFTOUT_MASK(mix->mask)); 331 nvol = __SHIFTOUT(val, mix->mask) << shift; 332 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = nvol; 333 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = nvol; 334 return 0; 335 336 case A64_CODEC_RECORD_SOURCE: 337 mc->un.mask = 338 a64_acodec_pr_read(sc, A64_L_ADCMIX_SRC) | 339 a64_acodec_pr_read(sc, A64_R_ADCMIX_SRC); 340 return 0; 341 } 342 343 return ENXIO; 344} 345 346static int 347a64_acodec_query_devinfo(void *priv, mixer_devinfo_t *di) 348{ 349 const struct a64_acodec_mixer *mix; 350 351 switch (di->index) { 352 case A64_CODEC_OUTPUT_CLASS: 353 di->mixer_class = di->index; 354 strcpy(di->label.name, AudioCoutputs); 355 di->type = AUDIO_MIXER_CLASS; 356 di->next = di->prev = AUDIO_MIXER_LAST; 357 return 0; 358 359 case A64_CODEC_INPUT_CLASS: 360 di->mixer_class = di->index; 361 strcpy(di->label.name, AudioCinputs); 362 di->type = AUDIO_MIXER_CLASS; 363 di->next = di->prev = AUDIO_MIXER_LAST; 364 return 0; 365 366 case A64_CODEC_RECORD_CLASS: 367 di->mixer_class = di->index; 368 strcpy(di->label.name, AudioCrecord); 369 di->type = AUDIO_MIXER_CLASS; 370 di->next = di->prev = AUDIO_MIXER_LAST; 371 return 0; 372 373 case A64_CODEC_OUTPUT_MASTER_VOLUME: 374 case A64_CODEC_OUTPUT_HP_VOLUME: 375 case A64_CODEC_INPUT_DAC_VOLUME: 376 case A64_CODEC_INPUT_LINEIN_VOLUME: 377 case A64_CODEC_INPUT_MIC1_VOLUME: 378 case A64_CODEC_INPUT_MIC2_VOLUME: 379 case A64_CODEC_RECORD_AGC_VOLUME: 380 mix = &a64_acodec_mixers[di->index]; 381 di->mixer_class = mix->mixer_class; 382 strcpy(di->label.name, mix->name); 383 di->un.v.delta = 384 256 / (__SHIFTOUT_MASK(mix->mask) + 1); 385 di->type = AUDIO_MIXER_VALUE; 386 di->next = di->prev = AUDIO_MIXER_LAST; 387 di->un.v.num_channels = 2; 388 strcpy(di->un.v.units.name, AudioNvolume); 389 return 0; 390 391 case A64_CODEC_RECORD_SOURCE: 392 di->mixer_class = A64_CODEC_RECORD_CLASS; 393 strcpy(di->label.name, AudioNsource); 394 di->type = AUDIO_MIXER_SET; 395 di->next = di->prev = AUDIO_MIXER_LAST; 396 di->un.s.num_mem = 4; 397 strcpy(di->un.s.member[0].label.name, AudioNline); 398 di->un.s.member[0].mask = A64_ADCMIX_SRC_LINEIN; 399 strcpy(di->un.s.member[1].label.name, "mic1"); 400 di->un.s.member[1].mask = A64_ADCMIX_SRC_MIC1; 401 strcpy(di->un.s.member[2].label.name, "mic2"); 402 di->un.s.member[2].mask = A64_ADCMIX_SRC_MIC2; 403 strcpy(di->un.s.member[3].label.name, AudioNdac); 404 di->un.s.member[3].mask = A64_ADCMIX_SRC_OMIXER; 405 return 0; 406 407 } 408 409 return ENXIO; 410} 411 412static const struct audio_hw_if a64_acodec_hw_if = { 413 .trigger_output = a64_acodec_trigger_output, 414 .trigger_input = a64_acodec_trigger_input, 415 .halt_output = a64_acodec_halt_output, 416 .halt_input = a64_acodec_halt_input, 417 .set_port = a64_acodec_set_port, 418 .get_port = a64_acodec_get_port, 419 .query_devinfo = a64_acodec_query_devinfo, 420}; 421 422static audio_dai_tag_t 423a64_acodec_dai_get_tag(device_t dev, const void *data, size_t len) 424{ 425 struct a64_acodec_softc * const sc = device_private(dev); 426 427 if (len != 4) 428 return NULL; 429 430 return &sc->sc_dai; 431} 432 433static struct fdtbus_dai_controller_func a64_acodec_dai_funcs = { 434 .get_tag = a64_acodec_dai_get_tag 435}; 436 437static int 438a64_acodec_dai_jack_detect(audio_dai_tag_t dai, u_int jack, int present) 439{ 440 struct a64_acodec_softc * const sc = audio_dai_private(dai); 441 const uint32_t lineout_mask = A64_LINEOUT_LEFT_EN | A64_LINEOUT_RIGHT_EN; 442 const uint32_t hppa_mask = A64_HPPA_EN; 443 444 switch (jack) { 445 case AUDIO_DAI_JACK_HP: 446 if (present) { 447 a64_acodec_pr_set_clear(sc, A64_LINEOUT_CTRL0, 448 0, lineout_mask); 449 a64_acodec_pr_set_clear(sc, A64_HP_CTRL, 450 hppa_mask, 0); 451 } else { 452 a64_acodec_pr_set_clear(sc, A64_LINEOUT_CTRL0, 453 lineout_mask, 0); 454 a64_acodec_pr_set_clear(sc, A64_HP_CTRL, 455 0, hppa_mask); 456 } 457 break; 458 case AUDIO_DAI_JACK_MIC: 459 /* XXX TODO */ 460 break; 461 } 462 463 return 0; 464} 465 466static const char * compatible[] = { 467 "allwinner,sun50i-a64-codec-analog", 468 NULL 469}; 470 471static int 472a64_acodec_match(device_t parent, cfdata_t cf, void *aux) 473{ 474 struct fdt_attach_args * const faa = aux; 475 476 return of_match_compatible(faa->faa_phandle, compatible); 477} 478 479static void 480a64_acodec_attach(device_t parent, device_t self, void *aux) 481{ 482 struct a64_acodec_softc * const sc = device_private(self); 483 struct fdt_attach_args * const faa = aux; 484 const int phandle = faa->faa_phandle; 485 bus_addr_t addr; 486 bus_size_t size; 487 488 sc->sc_dev = self; 489 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 490 aprint_error(": couldn't get registers\n"); 491 return; 492 } 493 sc->sc_bst = faa->faa_bst; 494 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 495 aprint_error(": couldn't map registers\n"); 496 return; 497 } 498 499 sc->sc_phandle = phandle; 500 501 aprint_naive("\n"); 502 aprint_normal(": A64 Audio Codec (analog part)\n"); 503 504 /* Right & Left Headphone PA enable */ 505 a64_acodec_pr_set_clear(sc, A64_HP_CTRL, 506 A64_HPPA_EN, 0); 507 508 /* Jack detect enable */ 509 a64_acodec_pr_set_clear(sc, A64_JACK_MIC_CTRL, 510 A64_JACKDETEN | A64_INNERRESEN | A64_AUTOPLEN, 0); 511 512 sc->sc_dai.dai_jack_detect = a64_acodec_dai_jack_detect; 513 sc->sc_dai.dai_hw_if = &a64_acodec_hw_if; 514 sc->sc_dai.dai_dev = self; 515 sc->sc_dai.dai_priv = sc; 516 fdtbus_register_dai_controller(self, phandle, &a64_acodec_dai_funcs); 517} 518 519CFATTACH_DECL_NEW(a64_acodec, sizeof(struct a64_acodec_softc), 520 a64_acodec_match, a64_acodec_attach, NULL, NULL); 521