exynos_wdt.c revision 1.8
1/* $NetBSD: exynos_wdt.c,v 1.8 2015/12/15 23:15:53 marty Exp $ */ 2 3/*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include "exynos_wdt.h" 33 34#include <sys/cdefs.h> 35__KERNEL_RCSID(0, "$NetBSD: exynos_wdt.c,v 1.8 2015/12/15 23:15:53 marty Exp $"); 36 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/cpu.h> 40#include <sys/device.h> 41#include <sys/wdog.h> 42 43#include <prop/proplib.h> 44 45#include <dev/sysmon/sysmonvar.h> 46 47#include <arm/samsung/exynos_io.h> 48#include <arm/samsung/exynos_reg.h> 49#include <arm/samsung/exynos_var.h> 50 51#include <dev/fdt/fdtvar.h> 52 53#if NEXYNOS_WDT > 0 54static int exynos_wdt_match(device_t, cfdata_t, void *); 55static void exynos_wdt_attach(device_t, device_t, void *); 56 57struct exynos_wdt_softc { 58 device_t sc_dev; 59 bus_space_tag_t sc_bst; 60 bus_space_handle_t sc_wdog_bsh; 61 struct sysmon_wdog sc_smw; 62 u_int sc_wdog_period; 63 u_int sc_wdog_clock_select; 64 u_int sc_wdog_prescaler; 65 uint32_t sc_freq; 66 uint32_t sc_wdog_wtdat; 67 uint32_t sc_wdog_wtcon; 68 bool sc_wdog_armed; 69}; 70 71#ifndef EXYNOS_WDT_PERIOD_DEFAULT 72#define EXYNOS_WDT_PERIOD_DEFAULT 60 73#endif 74 75CFATTACH_DECL_NEW(exynos_wdt, sizeof(struct exynos_wdt_softc), 76 exynos_wdt_match, exynos_wdt_attach, NULL, NULL); 77 78static inline uint32_t 79exynos_wdt_wdog_read(struct exynos_wdt_softc *sc, bus_size_t o) 80{ 81 return bus_space_read_4(sc->sc_bst, sc->sc_wdog_bsh, o); 82} 83 84static inline void 85exynos_wdt_wdog_write(struct exynos_wdt_softc *sc, bus_size_t o, uint32_t v) 86{ 87 bus_space_write_4(sc->sc_bst, sc->sc_wdog_bsh, o, v); 88} 89 90/* ARGSUSED */ 91static int 92exynos_wdt_match(device_t parent, cfdata_t cf, void *aux) 93{ 94 const char * const compatible[] = { "samsung,s3c2410-wdt", NULL }; 95 struct fdt_attach_args * const faa = aux; 96 97 return of_match_compatible(faa->faa_phandle, compatible); 98} 99 100static int 101exynos_wdt_tickle(struct sysmon_wdog *smw) 102{ 103 struct exynos_wdt_softc * const sc = smw->smw_cookie; 104 105 /* 106 * Cause the WDOG to restart counting. 107 */ 108 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 109 aprint_debug_dev(sc->sc_dev, "tickle\n"); 110 return 0; 111} 112 113static int 114exynos_wdt_setmode(struct sysmon_wdog *smw) 115{ 116 struct exynos_wdt_softc * const sc = smw->smw_cookie; 117 118 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 119 /* 120 * Emit magic sequence to turn off WDOG 121 */ 122 sc->sc_wdog_wtcon &= ~(WTCON_ENABLE|WTCON_RESET_ENABLE); 123 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 124 delay(1); 125 aprint_debug_dev(sc->sc_dev, "setmode disable\n"); 126 return 0; 127 } 128 129 /* 130 * If no changes, just tickle it and return. 131 */ 132 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) { 133 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1; 134 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE 135 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT) 136 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER); 137 138 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 139 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat); 140 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 141 aprint_debug_dev(sc->sc_dev, "setmode refresh\n"); 142 return 0; 143 } 144 145 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 146 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT; 147 smw->smw_period = EXYNOS_WDT_PERIOD_DEFAULT; 148 } 149 150 /* 151 * Make sure we don't overflow the counter. 152 */ 153 if (smw->smw_period * sc->sc_freq >= UINT16_MAX) { 154 return EINVAL; 155 } 156 157 sc->sc_wdog_wtdat = sc->sc_freq * sc->sc_wdog_period - 1; 158 sc->sc_wdog_wtcon = WTCON_ENABLE | WTCON_RESET_ENABLE 159 | __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT) 160 | __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER); 161 162 /* 163 * Have to disable to be able to write WTDAT 164 */ 165 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, 166 sc->sc_wdog_wtcon & ~(WTCON_ENABLE | WTCON_RESET_ENABLE)); 167 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCNT, sc->sc_wdog_wtdat); 168 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTDAT, sc->sc_wdog_wtdat); 169 exynos_wdt_wdog_write(sc, EXYNOS_WDT_WTCON, sc->sc_wdog_wtcon); 170 171 aprint_debug_dev(sc->sc_dev, "setmode enable\n"); 172 return 0; 173} 174 175 176static void 177exynos_wdt_attach(device_t parent, device_t self, void *aux) 178{ 179 struct exynos_wdt_softc * const sc = device_private(self); 180// prop_dictionary_t dict = device_properties(self); 181 struct fdt_attach_args * const faa = aux; 182 bus_addr_t addr; 183 bus_size_t size; 184 int error; 185 186 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 187 aprint_error(": couldn't get registers\n"); 188 return; 189 } 190 191 sc->sc_dev = self; 192 sc->sc_bst = faa->faa_bst; 193 194 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_wdog_bsh); 195 if (error) { 196 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 197 return; 198 } 199 200 /* 201 * This runs at the Exynos Pclk. 202 */ 203// prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 204 sc->sc_freq = 12000000; /* MJF: HACK hardwire for now */ 205 /* Need to figure out how to get freq from dtb */ 206 sc->sc_wdog_wtcon = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTCON); 207 sc->sc_wdog_armed = (sc->sc_wdog_wtcon & WTCON_ENABLE) 208 && (sc->sc_wdog_wtcon & WTCON_RESET_ENABLE); 209 if (sc->sc_wdog_armed) { 210 sc->sc_wdog_prescaler = 211 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER); 212 sc->sc_wdog_clock_select = 213 __SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT); 214 sc->sc_freq /= sc->sc_wdog_prescaler; 215 sc->sc_freq >>= 4 + sc->sc_wdog_clock_select; 216 sc->sc_wdog_wtdat = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTDAT); 217 sc->sc_wdog_period = (sc->sc_wdog_wtdat + 1) / sc->sc_freq; 218 } else { 219 sc->sc_wdog_period = EXYNOS_WDT_PERIOD_DEFAULT; 220 sc->sc_wdog_prescaler = 1; 221 /* 222 * Let's see what clock select we should use. 223 */ 224 u_int n = __builtin_ffs(sc->sc_freq) - 1; 225 if (n > 7) { 226 sc->sc_wdog_clock_select = WTCON_CLOCK_SELECT_128; 227 sc->sc_freq >>= 7; 228 } else if (n >= 4) { 229 sc->sc_wdog_clock_select = n - 4; 230 sc->sc_freq >>= n; 231 } 232 /* 233 * Let's hope the timer frequency isn't prime. If it is, find 234 * the highest divisor which gives us the least remainder. 235 */ 236 sc->sc_wdog_prescaler = 0; 237 u_int best_remainder = 256; 238 u_int max_period = 2 * EXYNOS_WDT_PERIOD_DEFAULT * sc->sc_freq; 239 for (size_t div = 256; UINT16_MAX > div * max_period; div++) { 240 u_int remainder = sc->sc_freq % div; 241 if (remainder == 0) { 242 sc->sc_wdog_prescaler = div; 243 break; 244 } 245 if (remainder < best_remainder) { 246 sc->sc_wdog_prescaler = div; 247 best_remainder = remainder; 248 } 249 } 250 KASSERT(sc->sc_wdog_prescaler != 0); 251 sc->sc_freq /= sc->sc_wdog_prescaler; 252 } 253 254 /* 255 * Does the config file tell us to turn on the watchdog? 256 */ 257 if (device_cfdata(self)->cf_flags & 1) 258 sc->sc_wdog_armed = true; 259 260 aprint_naive("\n"); 261 aprint_normal(": Exynos Watchdog Timer, default period is %u seconds%s\n", 262 sc->sc_wdog_period, 263 sc->sc_wdog_armed ? " (armed)" : ""); 264 265 sc->sc_smw.smw_name = device_xname(self); 266 sc->sc_smw.smw_cookie = sc; 267 sc->sc_smw.smw_setmode = exynos_wdt_setmode; 268 sc->sc_smw.smw_tickle = exynos_wdt_tickle; 269 sc->sc_smw.smw_period = sc->sc_wdog_period; 270 271 if (sc->sc_wdog_armed) { 272 error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 273 sc->sc_wdog_period); 274 if (error) 275 aprint_error_dev(self, 276 "failed to start kernel tickler: %d\n", error); 277 } 278} 279#endif /* NEXYNOS_WDOG > 0 */ 280 281void 282exynos_wdt_reset(void) 283{ 284 bus_space_tag_t bst = &exynos_bs_tag; 285 bus_space_handle_t bsh = exynos_wdt_bsh; 286 287 (void) splhigh(); 288 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON, 0); 289 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCNT, 1); 290 bus_space_write_4(bst, bsh, EXYNOS_WDT_WTCON, 291 WTCON_ENABLE | WTCON_RESET_ENABLE); 292} 293 294