1/* $NetBSD: exynos_usbphy.c,v 1.6 2021/01/27 03:10:19 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: exynos_usbphy.c,v 1.6 2021/01/27 03:10:19 thorpej Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/kmem.h>
39
40#include <dev/fdt/fdtvar.h>
41#include <dev/fdt/syscon.h>
42
43#include <arm/samsung/exynos_reg.h>
44#include <arm/samsung/exynos5_reg.h>
45
46/*
47 * System Registers
48 */
49#define	USB20PHY_CFG			0x230
50#define	 USB20PHY_CFG_HOST_LINK_EN	__BIT(0)
51
52/*
53 * PMU Registers
54 */
55#define	USBHOST_PHY_CTRL		0x708
56#define	 USBHOST_PHY_CTRL_EN		__BIT(0)
57
58enum {
59	PHY_ID_DEVICE = 0,
60	PHY_ID_HOST,
61	PHY_ID_HSIC0,
62	PHY_ID_HSIC1,
63	NPHY_ID
64};
65
66static int exynos_usbphy_match(device_t, cfdata_t, void *);
67static void exynos_usbphy_attach(device_t, device_t, void *);
68
69static const struct device_compatible_entry compat_data[] = {
70	{ .compat = "samsung,exynos5250-usb2-phy" },
71	DEVICE_COMPAT_EOL
72};
73
74struct exynos_usbphy_softc;
75
76struct exynos_usbphy {
77	struct exynos_usbphy_softc *phy_sc;
78	u_int			phy_index;
79};
80
81struct exynos_usbphy_softc {
82	device_t		sc_dev;
83	bus_space_tag_t		sc_bst;
84	bus_space_handle_t	sc_bsh;
85	int			sc_phandle;
86
87	struct syscon		*sc_sysreg;
88	struct syscon		*sc_pmureg;
89
90	u_int			sc_refcnt;
91
92	struct exynos_usbphy	*sc_phy;
93	u_int			sc_nphy;
94
95	struct fdtbus_gpio_pin	*sc_gpio_id_det;
96	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
97};
98
99#define	PHY_READ(sc, reg)				\
100	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
101#define	PHY_WRITE(sc, reg, val)				\
102	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
103
104CFATTACH_DECL_NEW(exynos_usbphy, sizeof(struct exynos_usbphy_softc),
105	exynos_usbphy_match, exynos_usbphy_attach, NULL, NULL);
106
107static void *
108exynos_usbphy_acquire(device_t dev, const void *data, size_t len)
109{
110	struct exynos_usbphy_softc * const sc = device_private(dev);
111
112	if (len != 4)
113		return NULL;
114
115	const u_int index = be32dec(data);
116	if (index >= sc->sc_nphy)
117		return NULL;
118
119	return &sc->sc_phy[index];
120}
121
122static void
123exynos_usbphy_release(device_t dev, void *priv)
124{
125}
126
127static int
128exynos_usbphy_enable(device_t dev, void *priv, bool enable)
129{
130	struct exynos_usbphy * const phy = priv;
131	struct exynos_usbphy_softc * const sc = phy->phy_sc;
132	bool do_common;
133	uint32_t val;
134
135	if (enable) {
136		sc->sc_refcnt++;
137	} else {
138		KASSERT(sc->sc_refcnt > 0);
139		sc->sc_refcnt--;
140	}
141	do_common = sc->sc_refcnt == enable;
142
143	if (do_common) {
144		syscon_lock(sc->sc_sysreg);
145		val = syscon_read_4(sc->sc_sysreg, USB20PHY_CFG);
146		if (enable)
147			val |= USB20PHY_CFG_HOST_LINK_EN;
148		else
149			val &= ~USB20PHY_CFG_HOST_LINK_EN;
150		syscon_write_4(sc->sc_sysreg, USB20PHY_CFG, val);
151		syscon_unlock(sc->sc_sysreg);
152
153		syscon_lock(sc->sc_pmureg);
154		val = syscon_read_4(sc->sc_pmureg, USBHOST_PHY_CTRL);
155		if (enable)
156			val |= USBHOST_PHY_CTRL_EN;
157		else
158			val &= ~USBHOST_PHY_CTRL_EN;
159		syscon_write_4(sc->sc_pmureg, USBHOST_PHY_CTRL, val);
160		syscon_unlock(sc->sc_pmureg);
161
162		if (enable) {
163			val = PHY_READ(sc, USB_PHY_HOST_CTRL0);
164			val &= ~HOST_CTRL0_COMMONON_N;
165			val &= ~HOST_CTRL0_PHY_SWRST;
166			val &= ~HOST_CTRL0_PHY_SWRST_ALL;
167			val &= ~HOST_CTRL0_SIDDQ;
168			val &= ~HOST_CTRL0_FORCESUSPEND;
169			val &= ~HOST_CTRL0_FORCESLEEP;
170			val &= ~HOST_CTRL0_FSEL_MASK;
171			val |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);
172			val |= HOST_CTRL0_LINK_SWRST;
173			val |= HOST_CTRL0_UTMI_SWRST;
174			PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
175
176			delay(10000);
177
178			val &= ~HOST_CTRL0_LINK_SWRST;
179			val &= ~HOST_CTRL0_UTMI_SWRST;
180			PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
181
182			delay(10000);
183		}
184	}
185
186	switch (phy->phy_index) {
187	case PHY_ID_HSIC0:
188	case PHY_ID_HSIC1:
189		if (enable) {
190			const bus_size_t reg = phy->phy_index == PHY_ID_HSIC0 ?
191			    USB_PHY_HSIC_CTRL1 : USB_PHY_HSIC_CTRL2;
192
193			val = HSIC_CTRL_PHY_SWRST;
194			val |= __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK);
195			val |= __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK);
196			PHY_WRITE(sc, reg, val);
197
198			delay(10000);
199
200			val &= ~HSIC_CTRL_PHY_SWRST;
201			PHY_WRITE(sc, reg, val);
202
203			delay(10000);
204		}
205		break;
206	}
207
208	if (do_common) {
209		if (enable) {
210			val = PHY_READ(sc, USB_PHY_HOST_EHCICTRL);
211			val |= HOST_EHCICTRL_ENA_INCRXALIGN;
212			val |= HOST_EHCICTRL_ENA_INCR4;
213			val |= HOST_EHCICTRL_ENA_INCR8;
214			val |= HOST_EHCICTRL_ENA_INCR16;
215			PHY_WRITE(sc, USB_PHY_HOST_EHCICTRL, val);
216		}
217	}
218
219	return 0;
220}
221
222const struct fdtbus_phy_controller_func exynos_usbphy_funcs = {
223	.acquire = exynos_usbphy_acquire,
224	.release = exynos_usbphy_release,
225	.enable = exynos_usbphy_enable,
226};
227
228static int
229exynos_usbphy_match(device_t parent, cfdata_t cf, void *aux)
230{
231	struct fdt_attach_args * const faa = aux;
232
233	return of_compatible_match(faa->faa_phandle, compat_data);
234}
235
236static void
237exynos_usbphy_attach(device_t parent, device_t self, void *aux)
238{
239	struct exynos_usbphy_softc * const sc = device_private(self);
240	struct fdt_attach_args * const faa = aux;
241	const int phandle = faa->faa_phandle;
242	struct clk *clk;
243	bus_addr_t addr;
244	bus_size_t size;
245	u_int n;
246
247	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
248		aprint_error(": couldn't get phy registers\n");
249		return;
250	}
251
252	sc->sc_dev = self;
253	sc->sc_phandle = phandle;
254	sc->sc_bst = faa->faa_bst;
255	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
256		aprint_error(": couldn't map phy registers\n");
257		return;
258	}
259	sc->sc_nphy = NPHY_ID;
260	sc->sc_phy = kmem_alloc(sizeof(*sc->sc_phy) * sc->sc_nphy, KM_SLEEP);
261	for (n = 0; n < sc->sc_nphy; n++) {
262		sc->sc_phy[n].phy_sc = sc;
263		sc->sc_phy[n].phy_index = n;
264	}
265
266	sc->sc_sysreg = fdtbus_syscon_acquire(phandle, "samsung,sysreg-phandle");
267	if (sc->sc_sysreg == NULL) {
268		aprint_error(": couldn't acquire sysreg syscon\n");
269		return;
270	}
271	sc->sc_pmureg = fdtbus_syscon_acquire(phandle, "samsung,pmureg-phandle");
272	if (sc->sc_pmureg == NULL) {
273		aprint_error(": couldn't acquire pmureg syscon\n");
274		return;
275	}
276
277	/* Enable clocks */
278	clk = fdtbus_clock_get(phandle, "phy");
279	if (clk == NULL || clk_enable(clk) != 0) {
280		aprint_error(": couldn't enable phy clock\n");
281		return;
282	}
283	clk = fdtbus_clock_get(phandle, "ref");
284	if (clk == NULL || clk_enable(clk) != 0) {
285		aprint_error(": couldn't enable ref clock\n");
286		return;
287	}
288
289	aprint_naive("\n");
290	aprint_normal(": USB2 PHY\n");
291
292	fdtbus_register_phy_controller(self, phandle, &exynos_usbphy_funcs);
293}
294