1/*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Fleischer <paul@xpg.dk> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* Derived from s3c2410reg.h */ 31 32/* 33 * Copyright (c) 2003, 2004 Genetec corporation. All rights reserved. 34 * Written by Hiroyuki Bessho for Genetec corporation. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of Genetec corporation may not be used to endorse 45 * or promote products derived from this software without specific prior 46 * written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 62/* 63 * Samsung S3C2440X processor is ARM920T based integrated CPU 64 * 65 * Reference: 66 * S3C2440X User's Manual 67 */ 68#ifndef _ARM_S3C2XX0_S3C2440REG_H_ 69#define _ARM_S3C2XX0_S3C2440REG_H_ 70 71/* common definitions for S3C2800, S3C2400 and S3C2410 */ 72#include <arm/s3c2xx0/s3c2xx0reg.h> 73/* common definitions for S3C2400 and S3C2410 */ 74#include <arm/s3c2xx0/s3c24x0reg.h> 75 76/* 77 * Memory Map 78 */ 79#define S3C2440_BANK_SIZE 0x08000000 80#define S3C2440_BANK_START(n) (S3C2440_BANK_SIZE*(n)) 81#define S3C2440_SDRAM_START S3C2440_BANK_START(6) 82 83/* 84 * Physical address of integrated peripherals 85 */ 86#define S3C2440_MEMCTL_BASE 0x48000000 /* memory controller */ 87#define S3C2440_USBHC_BASE 0x49000000 /* USB Host controller */ 88#define S3C2440_INTCTL_BASE 0x4a000000 /* Interrupt controller */ 89#define S3C2440_DMAC_BASE 0x4b000000 90#define S3C2440_DMAC_SIZE 0xe4 91#define S3C2440_CLKMAN_BASE 0x4c000000 /* clock & power management */ 92#define S3C2440_LCDC_BASE 0x4d000000 /* LCD controller */ 93#define S3C2440_NANDFC_BASE 0x4e000000 /* NAND Flash controller */ 94#define S3C2440_NANDFC_SIZE 0x18 95#define S3C2440_UART0_BASE 0x50000000 96#define S3C2440_UART_BASE(n) (S3C2440_UART0_BASE+0x4000*(n)) 97#define S3C2440_TIMER_BASE 0x51000000 98#define S3C2440_USBDC_BASE 0x5200140 99#define S3C2440_USBDC_SIZE 0x130 100#define S3C2440_WDT_BASE 0x53000000 101#define S3C2440_IIC_BASE 0x54000000 102#define S3C2440_IIS_BASE 0x55000000 103#define S3C2440_GPIO_BASE 0x56000000 104#define S3C2440_GPIO_SIZE 0xd0 105#define S3C2440_RTC_BASE 0x57000000 106#define S3C2440_RTC_SIZE 0x8B 107#define S3C2440_ADC_BASE 0x58000000 108#define S3C2440_ADC_SIZE 0x18 109#define S3C2440_SPI0_BASE 0x59000000 110#define S3C2440_SPI1_BASE 0x59000020 111#define S3C2440_SDI_BASE 0x5a000000 /* SD Interface */ 112#define S3C2440_SDI_SIZE 0x44 113 114/* interrupt control (additional defs for 2440) */ 115#define ICU_LEN (32+11) 116 117#define INTCTL_SUBSRCPND 0x18 /* sub source pending (2410+2440 only) */ 118#define INTCTL_INTSUBMSK 0x1c /* sub mask (2410+2440 only) */ 119 120/* 2440 has more than 32 interrupt sources. These are sub-sources 121 * that are OR-ed into main interrupt sources, and controlled via 122 * SUBSRCPND and SUBSRCMSK registers */ 123 124#define S3C2440_SUBIRQ_MIN 32 125#define S3C2440_SUBIRQ_MAX (32+10) 126 127/* cascaded to INT_ADCTC */ 128#define S3C2440_INT_ADC (S3C2440_SUBIRQ_MIN+10) /* AD converter */ 129#define S3C2440_INT_TC (S3C2440_SUBIRQ_MIN+9) /* Touch screen */ 130/* cascaded to INT_UART2 */ 131#define S3C2440_INT_ERR2 (S3C2440_SUBIRQ_MIN+8) /* UART2 Error interrupt */ 132#define S3C2440_INT_TXD2 (S3C2440_SUBIRQ_MIN+7) /* UART2 Tx interrupt */ 133#define S3C2440_INT_RXD2 (S3C2440_SUBIRQ_MIN+6) /* UART2 Rx interrupt */ 134/* cascaded to INT_UART1 */ 135#define S3C2440_INT_ERR1 (S3C2440_SUBIRQ_MIN+5) /* UART1 Error interrupt */ 136#define S3C2440_INT_TXD1 (S3C2440_SUBIRQ_MIN+4) /* UART1 Tx interrupt */ 137#define S3C2440_INT_RXD1 (S3C2440_SUBIRQ_MIN+3) /* UART1 Rx interrupt */ 138/* cascaded to INT_UART0 */ 139#define S3C2440_INT_ERR0 (S3C2440_SUBIRQ_MIN+2) /* UART0 Error interrupt */ 140#define S3C2440_INT_TXD0 (S3C2440_SUBIRQ_MIN+1) /* UART0 Tx interrupt */ 141#define S3C2440_INT_RXD0 (S3C2440_SUBIRQ_MIN+0) /* UART0 Rx interrupt */ 142 143#define S3C2440_INTCTL_SIZE 0x20 144 145 146/* Clock control */ 147#define CLKMAN_LOCKTIME 0x00 148#define CLKMAN_MPLLCON 0x04 149#define CLKMAN_UPLLCON 0x08 150#define CLKMAN_CLKCON 0x0c 151#define CLKCON_SPI (1<<18) 152#define CLKCON_IIS (1<<17) 153#define CLKCON_IIC (1<<16) 154#define CLKCON_ADC (1<<15) 155#define CLKCON_RTC (1<<14) 156#define CLKCON_GPIO (1<<13) 157#define CLKCON_UART2 (1<<12) 158#define CLKCON_UART1 (1<<11) 159#define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ 160#define CLKCON_SDI (1<<9) 161#define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ 162#define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ 163#define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ 164#define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ 165#define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ 166#define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ 167#define CLKCON_STOP (1<<0) /* 1=transition to STOP mode */ 168#define CLKMAN_CLKSLOW 0x10 169#define CLKMAN_CLKDIVN 0x14 170#define CLKDIVN_HDIVN_MASK 0x6 171#define CLKDIVN_HDIVN_SHIFT 1 172#define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */ 173#define CLKMAN_CAMDIVN 0x18 174#define CLKCAMDIVN_HCLK4_HALF (1<<8) /* Modifies HDIVN division rate if CLKDIVN[2:1] == 10b*/ 175#define CLKCAMDIVN_HCLK3_HALF (1<<9) /* Modifies HDIVN division rate if CLKDIVN[2:1] == 11b*/ 176 177/* NAND Flash controller */ 178#define NANDFC_NFCONF 0x00 /* Configuration */ 179#define NANDFC_NFCMD 0x08 /* command */ 180#define NANDFC_NFADDR 0x0C /* address */ 181#define NANDFC_NFDATA 0x10 /* data */ 182#define NANDFC_NFSTAT 0x20 /* operation status */ 183#define NANDFC_NFECC 0x34 /* ecc */ 184 185/* GPIO */ 186#define GPIO_PACON 0x00 /* port A configuration */ 187#define PCON_INPUT 0 /* Input port */ 188#define PCON_OUTPUT 1 /* Output port */ 189#define PCON_ALTFUN 2 /* Alternate function */ 190#define PCON_ALTFUN2 3 /* Alternate function */ 191#define GPIO_PADAT 0x04 /* port A data */ 192#define GPIO_PBCON 0x10 193#define GPIO_PBDAT 0x14 194#define GPIO_PBUP 0x18 195#define GPIO_PCCON 0x20 196#define GPIO_PCDAT 0x24 197#define GPIO_PCUP 0x28 198#define GPIO_PDCON 0x30 199#define GPIO_PDDAT 0x34 200#define GPIO_PDUP 0x38 201#define GPIO_PECON 0x40 202#define GPIO_PEDAT 0x44 203#define GPIO_PEUP 0x48 204#define GPIO_PFCON 0x50 205#define GPIO_PFDAT 0x54 206#define GPIO_PFUP 0x58 207#define GPIO_PGCON 0x60 208#define GPIO_PGDAT 0x64 209#define GPIO_PGUP 0x68 210#define GPIO_PHCON 0x70 211#define GPIO_PHDAT 0x74 212#define GPIO_PHUP 0x78 213#define GPIO_MISCCR 0x80 /* miscellaneous control */ 214#define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ 215#define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ 216#define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ 217#define GPIO_EINTMASK 0xa4 218#define GPIO_EINTPEND 0xa8 219#define GPIO_GSTATUS0 0xac /* external pin status */ 220#define GPIO_GSTATUS1 0xb0 /* external pin status */ 221 222#define GPIO_SET_FUNC(v,port,func) \ 223 (((v) & ~(3<<(2*(port))))|((func)<<(2*(port)))) 224#define GPIO_SET_DATA(v,pin,val) \ 225 ( ((v) & ~(1<<pin)) | (((val)&0x1)<<pin) ) 226 227#define EXTINTR_LOW 0x00 228#define EXTINTR_HIGH 0x01 229#define EXTINTR_FALLING 0x02 230#define EXTINTR_RISING 0x04 231#define EXTINTR_BOTH 0x06 232 233/* RTC */ 234#define RTC_RTCCON 0x40 235#define RTCCON_CLKRST (1<<3) 236#define RTCCON_CNTSEL (1<<2) 237#define RTCCON_CLKSEL (1<<1) 238#define RTCCON_RTCEN (1<<0) 239#define RTC_TICNT 0x44 240#define TICNT_INT 0x80 241#define TICNT_COUNT_MASK 0x7F 242#define RTC_BCDSEC 0x70 243#define RTC_BCDMIN 0x74 244#define RTC_BCDHOUR 0x78 245#define RTC_BCDDATE 0x7C 246#define RTC_BCDDAY 0x80 247#define RTC_BCDMON 0x84 248#define RTC_BCDYEAR 0x88 249 250/* UART */ 251#undef UFCON_TXTRIGGER_0 252#undef UFCON_TXTRIGGER_4 253#undef UFCON_TXTRIGGER_8 254#undef UFCON_TXTRIGGER_16 255#undef UFCON_RXTRIGGER_4 256#undef UFCON_RXTRIGGER_8 257#undef UFCON_RXTRIGGER_12 258#undef UFCON_RXTRIGGER_16 259#define UFCON_TXTRIGGER_0 (0<<6) 260#define UFCON_TXTRIGGER_16 (1<<6) 261#define UFCON_TXTRIGGER_32 (2<<6) 262#define UFCON_TXTRIGGER_48 (3<<6) 263#define UFCON_RXTRIGGER_1 (0<<4) 264#define UFCON_RXTRIGGER_8 (1<<4) 265#define UFCON_RXTRIGGER_16 (2<<4) 266#define UFCON_RXTRIGGER_32 (3<<4) 267#undef UFSTAT_TXFULL 268#define UFSTAT_TXFULL (1<<14) /* Tx fifo full */ 269#undef UFSTAT_RXFULL 270#define UFSTAT_RXFULL (1<<6) /* Rx fifo full */ 271#undef UFSTAT_TXCOUNT_SHIFT 272#undef UFSTAT_TXCOUNT 273#define UFSTAT_TXCOUNT_SHIFT 8 274#define UFSTAT_TXCOUNT (0x3f<<UFSTAT_TXCOUNT_SHIFT) 275#undef UFSTAT_RXCOUNT_SHIFT 276#undef UFSTAT_RXCOUNT 277#define UFSTAT_RXCOUNT_SHIFT 0 278#define UFSTAT_RXCOUNT (0x3f<<UFSTAT_RXCOUNT_SHIFT) 279 280 281/* SD interface */ 282#define SDI_CON 0x00 283#define SDICON_ENCLK (1<<0) 284#define SDICON_RWAIT_EN (1<<2) 285#define SDICON_RCV_IO_INT (1<<3) 286#define SDICON_BYTE_ORDER_A (0<<4) 287#define SDICON_BYTE_ORDER_B (1<<4) 288#define SDICON_CTYP_MMC (1<<5) 289#define SDICON_CTYP_SD (0<<5) 290#define SDICON_SD_RESET (1<<8) 291#define SDI_PRE 0x04 292#define SDI_CMD_ARG 0x08 293#define SDI_CMD_CON 0x0C 294#define SDICMDCON_CMD_MASK 0x3F 295#define SDICMDCON_HOST_CMD (1<<6) /* 01 in bits 6 and 7 */ 296#define SDICMDCON_CARD_RSP (0<<6) /* 00 in buts 6 and 8 */ 297#define SDICMDCON_CMST (1<<8) 298#define SDICMDCON_WAIT_RSP (1<<9) 299#define SDICMDCON_LONG_RSP (1<<10) 300#define SDICMDCON_WITH_DATA (1<<11) 301#define SDICMDCON_ABORT_CMD (1<<12) 302#define SDI_CMD_STA 0x10 303#define SDICMDSTA_RSP_MASK 0x03F 304#define SDICMDSTA_CMD_ON (1<<8) 305#define SDICMDSTA_RSP_FIN (1<<9) 306#define SDICMDSTA_CMD_TIMEOUT (1<<10) 307#define SDICMDSTA_CMD_SENT (1<<11) 308#define SDICMDSTA_RSP_CRC (1<<12) 309#define SDI_RSP0 0x14 310#define SDI_RSP1 0x18 311#define SDI_RSP2 0x1C 312#define SDI_RSP3 0x20 313#define SDI_DTIMER 0x24 314#define SDI_BSIZE 0x28 315#define SDI_DAT_CON 0x2C 316#define SDIDATCON_BLKNUM_MASK 0xFFF 317#define SDIDATCON_DATMODE_NOOP (0 << 12) 318#define SDIDATCON_DATMODE_BUSY (1 << 12) 319#define SDIDATCON_DATMODE_RECEIVE (2 << 12) 320#define SDIDATCON_DATMODE_TRANSMIT (3 << 12) 321#define SDIDATCON_DTST (1 << 14) 322#define SDIDATCON_ENDMA (1 << 15) 323#define SDIDATCON_WIDEBUS (1 << 16) 324#define SDIDATCON_BLKMODE (1 << 17) 325#define SDIDATCON_BACMD (1 << 18) 326#define SDIDATCON_RACMD (1 << 19) 327#define SDIDATCON_TARSP (1 << 20) 328#define SDIDATCON_PRD_TYPE (1 << 21) 329#define SDIDATCON_DATA_BYTE (0 << 22) 330#define SDIDATCON_DATA_HALFWORD (1 << 22) 331#define SDIDATCON_DATA_WORD (2 << 22) 332#define SDIDATCON_BURST4 (1 << 24) 333#define SDI_DAT_CNT 0x30 334#define SDIDATCNT_BLK_CNT_MASK 0xFFF 335#define SDIDATCNT_BLK_CNT(reg) (reg & SDIDATCON_BLKNUM_MASK) 336#define SDIDATCNT_BLK_NUM_CNT_MASK 0xFFF000 337#define SDIDATCNT_BLK_NUM_CNT_SHIFT 12 338#define SDIDATCNT_BLK_NUM_CNT(reg) ( (reg & SDIDATCNT_BLK_NUM_CNT_MASK) >> SDIDATCNT_BLK_NUM_CNT_SHIFT) 339#define SDI_DAT_STA 0x34 340#define SDIDATSTA_RX (1 << 0) 341#define SDIDATSTA_TX (1 << 1) 342#define SDIDATSTA_BUSY_FIN (1 << 3) 343#define SDIDATSTA_DATA_FIN (1 << 4) 344#define SDIDATSTA_DATA_TIMEOUT (1 << 5) 345#define SDIDATSTA_CRC_DAT_FAIL (1 << 6) 346#define SDIDATSTA_CRC_STATUS_FAIL (1 << 7) 347#define SDIDATSTA_SDIO_INT (1 << 9) 348#define SDIDATSTA_RWAIT_REQ (1 << 10) 349#define SDIDATSTA_NO_BUSY (1 << 11) 350#define SDI_DAT_FSTA 0x38 351#define SDIDATFSTA_FFCNT_MASK 0x7F 352#define SDIDATFSTA_FFCNT(reg) (reg & SDIDATFSTA_FFCNT_MASK) 353#define SDIDATFSTA_RF_HALF (1 << 7) 354#define SDIDATFSTA_RF_FULL (1 << 8) 355#define SDIDATFSTA_RF_LAST (1 << 9) 356#define SDIDATFSTA_TF_EMPTY (1 << 10) 357#define SDIDATFSTA_TF_HALF (1 << 11) 358#define SDIDATFSTA_RF_DETECT (1 << 12) 359#define SDIDATFSTA_TX_DETECT (1 << 13) 360#define SDIDATFSTA_FAIL_NO_DETECT (0 << 14) 361#define SDIDATFSTA_FAIL_FIFO (1 << 14) 362#define SDIDATFSTA_FAIL_FIFO_LAST (2 << 14) 363#define SDIDATFSTA_RESET (1 << 16) 364#define SDI_INT_MASK 0x3C 365#define SDIINTMASK_RF_HALF (1<<0) 366#define SDIINTMASK_RF_FULL (1<<1) 367#define SDIINTMASK_RF_LAST (1<<2) 368#define SDIINTMASK_TF_EMPTY (1<<3) 369#define SDIINTMASK_TF_HALF (1<<4) 370#define SDIINTMASK_BUSY_FIN (1<<6) 371#define SDIINTMASK_DATA_FIN (1<<7) 372#define SDIINTMASK_DATA_TIMEOUT (1<<8) 373#define SDIINTMASK_DATA_CRC (1<<9) 374#define SDIINTMASK_STATUS_CRC (1<<10) 375#define SDIINTMASK_FIFO_FAIL (1<<11) 376#define SDIINTMASK_IO (1<<12) 377#define SDIINTMASK_READ_WAIT (1<<13) 378#define SDIINTMASK_RESP (1<<14) 379#define SDIINTMASK_CMD_TIMEOUT (1<<15) 380#define SDIINTMASK_CMD_SENT (1<<16) 381#define SDIINTMASK_RESP_CRC (1<<17) 382#define SDIINTMASK_NO_BUSY (1<<18) 383#define SDI_DAT_LI_W 0x40 /* Word access in Little Endian mode */ 384#define SDI_DAT_LI_HW 0x44 /* Half-Word access in Little Endian mode */ 385#define SDI_DAT_LI_B 0x48 /* Byte access in Little Endian mode */ 386#define SDI_DAT_BI_W 0x4C /* Word access in Big Endian mode */ 387#define SDI_DAT_BI_HW 0x41 /* Half-Word access in Big Endian mode */ 388#define SDI_DAT_BI_B 0x43 /* Byte access in Big Endian mode */ 389 390/* ADC */ 391/* XXX: ADCCON register is common to both S3C2410 and S3C2400, 392 * but other registers are different. 393 */ 394#define ADC_ADCCON 0x00 395#define ADCCON_ENABLE_START (1<<0) 396#define ADCCON_READ_START (1<<1) 397#define ADCCON_STDBM (1<<2) 398#define ADCCON_SEL_MUX_SHIFT 3 399#define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT) 400#define ADCCON_PRSCVL_SHIFT 6 401#define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT) 402#define ADCCON_PRSCEN (1<<14) 403#define ADCCON_ECFLG (1<<15) 404 405#define ADC_ADCTSC 0x04 406#define ADCTSC_XY_PST 0x03 407#define ADCTSC_AUTO_PST (1<<2) 408#define ADCTSC_PULL_UP (1<<3) 409#define ADCTSC_XP_SEN (1<<4) 410#define ADCTSC_XM_SEN (1<<5) 411#define ADCTSC_YP_SEN (1<<6) 412#define ADCTSC_YM_SEN (1<<7) 413#define ADCTSC_UD_SEN (1<<8) 414#define ADC_ADCDLY 0x08 415#define ADC_ADCDAT0 0x0c 416#define ADC_ADCDAT1 0x10 417#define ADC_ADCUPDN 0x14 418#define ADCUPDN_TSC_DN (1<<0) 419#define ADCUPDN_TSC_UP (1<<1) 420 421 422#define ADCDAT_DATAMASK 0x3ff 423 424/* DMA */ 425#define S3C2440_DMA_CHANNELS 4 426#define S3C2440_DMA_SIZE 0x40 427#define DMA_OFFSET(ch) ch*S3C2440_DMA_SIZE 428#define DMA_DISRC_BASE 0x000000 429#define DMA_DISRC(ch) (DMA_DISRC_BASE+DMA_OFFSET(ch)) 430#define DISRC_MASK 0x7FFFFFFF /* Only 31 bits are used */ 431#define DMA_DISRCC_BASE 0x000004 432#define DMA_DISRCC(ch) (DMA_DISRCC_BASE+DMA_OFFSET(ch)) 433#define DISRCC_INC_INC (0<<0) 434#define DISRCC_INC_FIXED (1<<0) 435#define DISRCC_LOC_AHB (0<<1) 436#define DISRCC_LOC_APB (1<<1) 437#define DMA_DIDST_BASE 0x000008 438#define DMA_DIDST(ch) (DMA_DIDST_BASE+DMA_OFFSET(ch)) 439#define DIDST_MASK 0x7FFFFFFF /* Only 31 bits are used */ 440#define DMA_DIDSTC_BASE 0x00000C 441#define DMA_DIDSTC(ch) (DMA_DIDSTC_BASE+DMA_OFFSET(ch)) 442#define DIDSTC_INC_INC (0<<0) 443#define DIDSTC_INC_FIXED (1<<0) 444#define DIDSTC_LOC_AHB (0<<1) 445#define DIDSTC_LOC_APB (1<<1) 446#define DIDSTC_INT_TC (0<<2) 447#define DIDSTC_INT_AUTO_RELOAD (1<<2) 448#define DMA_CON_BASE 0x000010 449#define DMA_CON(ch) (DMA_CON_BASE+DMA_OFFSET(ch)) 450#define DMACON_TC_MASK 0xFFFFF 451#define DMACON_TC(val) (val & DMACON_TC_MASK) 452#define DMACON_DSZ_B (0<<20) 453#define DMACON_DSZ_HW (1<<20) 454#define DMACON_DSZ_W (2<<20) 455#define DMACON_RELOAD_AUTO (0<<22) 456#define DMACON_RELOAD_NO_AUTO (1<<22) 457#define DMACON_SW_REQ (0<<23) 458#define DMACON_HW_REQ (1<<23) 459#define DMACON_HW_SRCSEL_MASK (0x7) 460#define DMACON_HW_SRCSEL_SHIFT 24 461#define DMACON_HW_SRCSEL(v) ( (v & DMACON_HW_SRCSEL_MASK) << DMACON_HW_SRCSEL_SHIFT) 462#define DMACON_SERVMODE_SINGLE (0<<27) 463#define DMACON_SERVMODE_WHOLE (1<<27) 464#define DMACON_TSZ_UNIT (0<<28) 465#define DMACON_TSZ_BURST (1<<28) 466#define DMACON_INT_POLL (0<<29) 467#define DMACON_INT_INT (1<<29) 468#define DMACON_SYNC_APB (0<<30) 469#define DMACON_SYNC_AHB (1<<30) 470#define DMACON_DEMAND (0<<31) 471#define DMACON_HANDSHAKE (1<<31) 472#define DMA_STAT_BASE 0x000014 473#define DMA_STAT(ch) (DMA_STAT_BASE + DMA_OFFSET(ch)) 474#define DMASTAT_CURR_TC_MASK 0xFFFFF 475#define DMASTAT_CURR_TC(v) (DMASTAT_CURR_TC_MASK & v) 476#define DMASTAT_BUSY (1<<20) 477#define DMA_CSRC_BASE 0x000018 478#define DMA_CSRC(ch) (DMA_CSRC_BASE + DMA_OFFSET(ch)) 479#define DMA_CDST_BASE 0x00001C 480#define DMA_CDST(ch) (DMA_CDST_BASE + DMA_OFFSET(ch)) 481#define DMA_MASKTRIG_BASE 0x000020 482#define DMA_MASKTRIG(ch) (DMA_MASKTRIG_BASE + DMA_OFFSET(ch)) 483#define DMAMASKTRIG_SW_TRIG (1<<0) 484#define DMAMASKTRIG_HW_TRIG (0<<0) 485#define DMAMASKTRIG_OFF (0<<1) 486#define DMAMASKTRIG_ON (1<<1) 487#define DMAMASKTRIG_STOP (1<<2) 488 489#define IISCON 0x0 490#define IISCON_IFACE_EN (1<<0) 491#define IISCON_PRESCALER_EN (1<<1) 492#define IISCON_RX_IDLE (1<<2) 493#define IISCON_TX_IDLE (1<<3) 494#define IISCON_RX_DMA_EN (1<<4) 495#define IISCON_TX_DMA_EN (1<<5) 496#define IISCON_RX_FIFO_RDY (1<<6) 497#define IISCON_TX_FIFO_RDY (1<<7) 498#define IISCON_CHANNEL_RIGHT (1<<8) 499#define IISMOD 0x04 500#define IISMOD_SERIAL_FREQ_MASK (0x03) 501#define IISMOD_SERIAL_FREQ_SHIFT (0) 502#define IISMOD_SERIAL_FREQ(val) ((val << IISMOD_SERIAL_FREQ_SHIFT) & IISMOD_SERIAL_FREQ_MASK) 503#define IISMOD_SERIAL_FREQ16 IISMOD_SERIAL_FREQ(0) 504#define IISMOD_SERIAL_FREQ32 IISMOD_SERIAL_FREQ(1) 505#define IISMOD_SERIAL_FREQ48 IISMOD_SERIAL_FREQ(2) 506#define IISMOD_MASTER_FREQ256 (0<<2) 507#define IISMOD_MASTER_FREQ384 (1<<2) 508#define IISMOD_16BIT (1<<3) 509#define IISMOD_IFACE_MSB (1<<4) 510#define IISMOD_LEFT_HIGH (1<<5) 511#define IISMOD_MODE_MASK (0xC0) 512#define IISMOD_MODE_SHIFT (6) 513 514#if 0 515#define IISMOD_MODE(val) ((val << IISMOD_MODE_SHIFT) & IISMOD_MODE_MASK) 516#define IISMOD_MODE_NO_XFER IISMOD_MODE(0) 517#define IISMOD_MODE_RECEIVE IISMOD_MODE(1) 518#define IISMOD_MODE_TRANSMIT IISMOD_MODE(2) 519#define IISMOD_MODE_BOTH IISMOD_MODE(3) 520#endif 521#define IISMOD_MODE_RECEIVE (1<<6) 522#define IISMOD_MODE_TRANSMIT (1<<7) 523#define IISMOD_SLAVE (1<<8) 524#define IISMOD_CLOCK_MPLL (1<<9) 525#define IISPSR 0x08 526#define IISPSR_PRESCALER_A_MASK (0x3E0) 527#define IISPSR_PRESCALER_A_SHIFT (5) 528#define IISPSR_PRESCALER_A(val) (((val) << IISPSR_PRESCALER_A_SHIFT) & IISPSR_PRESCALER_A_MASK) 529#define IISPSR_PRESCALER_B_MASK (0x1F) 530#define IISPSR_PRESCALER_B_SHIFT (0) 531#define IISPSR_PRESCALER_B(val) (((val) << IISPSR_PRESCALER_B_SHIFT) & IISPSR_PRESCALER_B_MASK) 532#define IISFCON 0x0C 533#define IISFCON_RX_COUNT_MASK (0x3F) 534#define IISFCON_RX_COUNT_SHIFT 0 535#define IISFCON_TX_COUNT_MASK (0xFC0) 536#define IISFCON_TX_COUNT_SHIFT 6 537#define IISFCON_RX_FIFO_EN (1<<12) 538#define IISFCON_TX_FIFO_EN (1<<13) 539#define IISFCON_RX_DMA_EN (1<<14) 540#define IISFCON_TX_DMA_EN (1<<15) 541#define IISFIFO 0x10 542#define IISFIFO_FENTRY_MASK (0xFFFF) 543 544 545#endif /* _ARM_S3C2XX0_S3C2440REG_H_ */ 546