1/* $NetBSD: imx6_reg.h,v 1.2 2023/05/04 13:28:04 bouyer Exp $ */ 2 3/*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ARM_NXP_IMX6_REG_H_ 33#define _ARM_NXP_IMX6_REG_H_ 34 35#define IMX6_IOREG_PBASE IMX6_AIPS1_BASE 36#define IMX6_IOREG_SIZE (IMX6_AIPS1_SIZE + IMX6_AIPS2_SIZE) 37#define IMX6SX_IOREG_SIZE (IMX6_AIPS1_SIZE + IMX6_AIPS2_SIZE + IMX6_AIPS3_SIZE) 38 39#define IMX6_ARMCORE_PBASE IMX6_MPCORE_BASE 40#define IMX6_ARMCORE_SIZE IMX6_MPCORE_SIZE 41 42#define IMX6_IO_SIZE (IMX6_IOREG_SIZE + IMX6_ARMCORE_SIZE) 43 44#define ARMCORE_SCU_BASE 0x00000000 45#define ARMCORE_L2C_BASE 0x00002000 46 47#define IMX6_MEM_BASE 0x10000000 48#define IMX6_MEM_SIZE 0xF0000000 49 50#define IMX6_CS0_BASE 0x08000000 51#define IMX6_CS0_SIZE 0x08000000 52 53#define IMX6_IPU2_BASE 0x02a00000 54#define IMX6_IPU1_BASE 0x02600000 55#define IMX6_IPU_SIZE 0x00400000 56 57#define IMX6_HSI_BASE 0x02208000 58#define IMX6_HSI_SIZE 0x00004000 59 60#define IMX6_OPENVG_BASE 0x02204000 61#define IMX6_OPENVG_SIZE 0x00004000 62 63#define IMX6_SATA_BASE 0x02200000 64#define IMX6_SATA_SIZE 0x00004000 65 66#define IMX6_AIPS3_BASE 0x02200000 67#define IMX6_AIPS3_SIZE 0x00100000 68 69#define IMX6_AIPS2_BASE 0x02100000 70#define IMX6_AIPS2_SIZE 0x00100000 71 72#define IMX6_AIPS1_BASE 0x02000000 73#define IMX6_AIPS1_SIZE 0x00100000 74 75#define IMX6_PCIE_BASE 0x01ffc000 76#define IMX6_PCIE_SIZE 0x00004000 77 78#define IMX6_PCIEMEM_BASE 0x01000000 79#define IMX6_PCIEMEM_SIZE 0x00ffc000 80 81#define IMX6_GPV1_BASE 0x00c00000 82#define IMX6_GPV1_SIZE 0x00100000 83 84#define IMX6_GPV0_BASE 0x00b00000 85#define IMX6_GPV0_SIZE 0x00100000 86 87#define IMX6_L2CC_BASE 0x00a02000 88#define IMX6_L2CC_SIZE 0x00001000 89 90#define IMX6_MPCORE_BASE 0x00a00000 91#define IMX6_MPCORE_SIZE 0x00100000 92 93#define IMX6_OCRAM1_BASE 0x00940000 94#define IMX6_OCRAM1_SIZE 0x000c0000 95 96#define IMX6_OCRAM0_BASE 0x00900000 97#define IMX6_OCRAM0_SIZE 0x00040000 98 99#define IMX6_GPV4_BASE 0x00800000 100#define IMX6_GPV4_SIZE 0x00100000 101 102#define IMX6_GPV3_BASE 0x00300000 103#define IMX6_GPV3_SIZE 0x00100000 104 105#define IMX6_GPV2_BASE 0x00200000 106#define IMX6_GPV2_SIZE 0x00100000 107 108#define IMX6_DTPC_BASE 0x00138000 109#define IMX6_DTPC_SIZE 0x00004000 110 111#define IMX6_GPU2D_BASE 0x00134000 112#define IMX6_GPU2D_SIZE 0x00004000 113 114#define IMX6_GPU3D_BASE 0x00130000 115#define IMX6_GPU3D_SIZE 0x00004000 116 117#define IMX6_HDMI_BASE 0x00120000 118#define IMX6_HDMI_SIZE 0x00009000 119 120#define IMX6_APBHDMA_BASE 0x00110000 121#define IMX6_APBHDMA_SIZE 0x00002000 122 123#define IMX6_GPMI_BASE 0x00112000 124#define IMX6_GPMI_SIZE 0x00002000 125 126#define IMX6_BCH_BASE 0x00114000 127#define IMX6_BCH_SIZE 0x00004000 128 129#define IMX6_CAAM_BASE 0x00100000 130#define IMX6_CAAM_SIZE 0x00004000 131 132#define IMX6_ROMCP_BASE 0x00000000 133#define IMX6_ROMCP_SIZE 0x00018000 134 135#define AIPS1_SDMA_BASE 0x000ec000 136#define AIPS1_DCIC2_BASE 0x000e8000 137#define AIPS1_DCIC1_BASE 0x000e4000 138#define AIPS1_IOMUXC_BASE 0x000e0000 139#define AIPS1_IOMUXC_SIZE 0x00004000 140#define AIPS1_GPC_BASE 0x000dc000 141#define AIPS1_SRC_BASE 0x000d8000 142#define AIPS1_SRC_SIZE 0x00004000 143#define AIPS1_EPIT2_BASE 0x000d4000 144#define AIPS1_EPIT1_BASE 0x000d0000 145#define AIPS1_EPIT_SIZE 0x00000020 146#define AIPS1_SNVS_BASE 0x000cc000 147#define AIPS1_SNVS_SIZE 0x00000c00 148#define AIPS1_USBPHY2_BASE 0x000ca000 149#define AIPS1_USBPHY1_BASE 0x000c9000 150#define AIPS1_USBPHY_SIZE 0x00001000 151 152#define AIPS1_CCM_BASE 0x000c4000 153#define AIPS1_CCM_SIZE 0x00004000 154 155#define AIPS1_WDOG2_BASE 0x000c0000 156#define AIPS1_WDOG1_BASE 0x000bc000 157#define AIPS1_WDOG_SIZE 0x00000010 158#define AIPS1_KPP_BASE 0x000b8000 159#define AIPS1_ENET2_BASE 0x000b4000 /* iMX6UL */ 160#define AIPS1_GPIO7_BASE 0x000b4000 161#define AIPS1_GPIO6_BASE 0x000b0000 162#define AIPS1_GPIO5_BASE 0x000ac000 163#define AIPS1_GPIO4_BASE 0x000a8000 164#define AIPS1_GPIO3_BASE 0x000a4000 165#define AIPS1_GPIO2_BASE 0x000a0000 166#define AIPS1_GPIO1_BASE 0x0009c000 167#define GPIO_NGROUPS 7 168#define AIPS1_GPT_BASE 0x00098000 169#define AIPS1_CAN2_BASE 0x00094000 170#define AIPS1_CAN1_BASE 0x00090000 171#define AIPS1_PWM4_BASE 0x0008c000 172#define AIPS1_PWM3_BASE 0x00088000 173#define AIPS1_PWM2_BASE 0x00084000 174#define AIPS1_PWM1_BASE 0x00080000 175#define AIPS1_CONFIG_BASE 0x0007c000 176#define AIPS1_VPU_BASE 0x00040000 177#define AIPS1_SPBA_BASE 0x0003c000 178#define AIPS1_ASRC_BASE 0x00034000 179#define AIPS1_SSI3_BASE 0x00030000 180#define AIPS1_SSI2_BASE 0x0002c000 181#define AIPS1_SSI1_BASE 0x00028000 182#define AIPS1_ESAI_BASE 0x00024000 183#define AIPS1_UART1_BASE 0x00020000 184#define AIPS1_UART7_BASE 0x00018000 /* iMX6UL */ 185#define AIPS1_ECSPI5_BASE 0x00018000 186#define AIPS1_ECSPI4_BASE 0x00014000 187#define AIPS1_ECSPI3_BASE 0x00010000 188#define AIPS1_ECSPI2_BASE 0x0000c000 189#define AIPS1_ECSPI1_BASE 0x00008000 190#define AIPS1_SPDIF_BASE 0x00004000 191 192#define AIPS2_UART6_BASE 0x000fc000 /* iMX6UL */ 193#define AIPS2_UART5_BASE 0x000f4000 194#define AIPS2_UART4_BASE 0x000f0000 195#define AIPS2_UART3_BASE 0x000ec000 196#define AIPS2_UART2_BASE 0x000e8000 197#define AIPS2_WDOG3_BASE 0x000e4000 /* iMX6UL */ 198#define AIPS2_VDOA_BASE 0x000e3000 199#define AIPS2_MIPIDSI_BASE 0x000e0000 200#define AIPS2_MIPICSI_BASE 0x000dc000 201#define AIPS2_AUDMUX_BASE 0x000d8000 202#define AIPS2_TZASC2_BASE 0x000d4000 203#define AIPS2_TZASC1_BASE 0x000d0000 204#define AIPS2_CSU_BASE 0x000c0000 205#define AIPS2_OCOTP_CTRL_BASE 0x000bc000 206#define AIPS2_OCOTP_CTRL_SIZE 0x00000700 207#define AIPS2_WEIM_BASE 0x000b8000 208#define AIPS2_MMDC2_BASE 0x000b4000 209#define AIPS2_MMDC1_BASE 0x000b0000 210#define AIPS2_ROMCP_BASE 0x000ac000 211 212#define AIPS2_I2C3_BASE 0x000a8000 213#define AIPS2_I2C2_BASE 0x000a4000 214#define AIPS2_I2C1_BASE 0x000a0000 215#define I2C_SIZE 0x4000 216 217#define AIPS2_USDHC4_BASE 0x0009c000 218#define AIPS2_USDHC3_BASE 0x00098000 219#define AIPS2_USDHC2_BASE 0x00094000 220#define AIPS2_USDHC1_BASE 0x00090000 221#define AIPS2_USDHC_SIZE 0x000000d0 222#define AIPS2_MLB150_BASE 0x0008c000 223#define AIPS2_ENET_BASE 0x00088000 224#define AIPS2_USBOH_BASE 0x00084000 225#define AIPS2_USBOH_SIZE 0x00000800 226#define AIPS2_CONFIG_BASE 0x0007c000 227#define AIPS2_DAP_BASE 0x00040000 228#define AIPS2_CAAM_BASE 0x00000000 229 230#endif /* _ARM_NXP_IMX6_REG_H_ */ 231