imx6_pcie.c revision 1.6 
1/*	$NetBSD: imx6_pcie.c,v 1.6 2021/01/27 03:10:20 thorpej Exp $	*/
2
3/*-
4 * Copyright (c) 2019 Genetec Corporation.  All rights reserved.
5 * Written by Hashimoto Kenichi for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.6 2021/01/27 03:10:20 thorpej Exp $");
31
32#include "opt_pci.h"
33#include "opt_fdt.h"
34
35#include "pci.h"
36#include "locators.h"
37
38#define	_INTR_PRIVATE
39
40#include <sys/bus.h>
41#include <sys/device.h>
42#include <sys/intr.h>
43#include <sys/systm.h>
44#include <sys/param.h>
45#include <sys/kernel.h>
46#include <sys/queue.h>
47#include <sys/mutex.h>
48#include <sys/kmem.h>
49#include <sys/gpio.h>
50
51#include <machine/frame.h>
52#include <arm/cpufunc.h>
53
54#include <dev/fdt/fdtvar.h>
55
56#include <dev/pci/pcireg.h>
57#include <dev/pci/pcivar.h>
58#include <dev/pci/pciconf.h>
59
60#include <arm/imx/imxpcievar.h>
61#include <arm/imx/imxgpioreg.h>
62#include <arm/imx/imxgpiovar.h>
63#include <arm/nxp/imx6_iomuxreg.h>
64#include <arm/nxp/imx6_ccmreg.h>
65#include <arm/nxp/imx6_ccmvar.h>
66
67struct imxpcie_fdt_softc {
68	struct imxpcie_softc sc_imxpcie;
69
70	struct fdtbus_gpio_pin	*sc_pin_reset;
71	struct fdtbus_regulator	*sc_reg_vpcie;
72};
73
74static int imx6_pcie_match(device_t, cfdata_t, void *);
75static void imx6_pcie_attach(device_t, device_t, void *);
76
77static void imx6_pcie_configure(void *);
78static uint32_t imx6_pcie_gpr_read(void *, uint32_t);
79static void imx6_pcie_gpr_write(void *, uint32_t, uint32_t);
80static void imx6_pcie_reset(void *);
81
82#define IMX6_PCIE_MEM_BASE	0x01000000
83#define IMX6_PCIE_MEM_SIZE	0x00f00000 /* 15MB */
84#define IMX6_PCIE_ROOT_BASE	0x01f00000
85#define IMX6_PCIE_ROOT_SIZE	0x00080000 /* 512KB */
86#define IMX6_PCIE_IO_BASE	0x01f80000
87#define IMX6_PCIE_IO_SIZE	0x00010000 /* 64KB */
88
89CFATTACH_DECL_NEW(imxpcie_fdt, sizeof(struct imxpcie_fdt_softc),
90    imx6_pcie_match, imx6_pcie_attach, NULL, NULL);
91
92static const struct device_compatible_entry compat_data[] = {
93	{ .compat = "fsl,imx6q-pcie",	.value = false },
94	{ .compat = "fsl,imx6qp-pcie",	.value = true },
95	DEVICE_COMPAT_EOL
96};
97
98static int
99imx6_pcie_match(device_t parent, cfdata_t cf, void *aux)
100{
101	struct fdt_attach_args * const faa = aux;
102
103	return of_compatible_match(faa->faa_phandle, compat_data);
104}
105
106static void
107imx6_pcie_attach(device_t parent, device_t self, void *aux)
108{
109	struct imxpcie_fdt_softc * const ifsc = device_private(self);
110	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
111	struct fdt_attach_args * const faa = aux;
112	const int phandle = faa->faa_phandle;
113	bus_space_tag_t bst = faa->faa_bst;
114	char intrstr[128];
115	bus_addr_t addr;
116	bus_size_t size;
117
118	aprint_naive("\n");
119	aprint_normal(": PCI Express Controller\n");
120
121	sc->sc_dev = self;
122	sc->sc_iot = bst;
123	sc->sc_dmat = faa->faa_dmat;
124	sc->sc_cookie = ifsc;
125	sc->sc_pci_netbsd_configure = imx6_pcie_configure;
126	sc->sc_gpr_read = imx6_pcie_gpr_read;
127	sc->sc_gpr_write = imx6_pcie_gpr_write;
128	sc->sc_reset = imx6_pcie_reset;
129	sc->sc_have_sw_reset =
130	    (bool)of_compatible_lookup(phandle, compat_data)->value;
131
132	if (fdtbus_get_reg_byname(phandle, "dbi", &addr, &size) != 0) {
133		aprint_error(": couldn't get registers\n");
134		return;
135	}
136	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) {
137		aprint_error_dev(self, "Cannot map registers\n");
138		return;
139	}
140	if (fdtbus_get_reg_byname(phandle, "config", &addr, &size) != 0) {
141		aprint_error(": couldn't get registers\n");
142		return;
143	}
144	sc->sc_root_addr = addr;
145	sc->sc_root_size = size;
146
147	const int gpr_phandle = OF_finddevice("/soc/aips-bus/iomuxc-gpr");
148	fdtbus_get_reg(gpr_phandle, 0, &addr, &size);
149	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_gpr_ioh)) {
150		aprint_error_dev(self, "Cannot map registers\n");
151		return;
152	}
153
154	ifsc->sc_pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpio",
155	    GPIO_PIN_OUTPUT);
156	if (!ifsc->sc_pin_reset) {
157		aprint_error(": couldn't acquire reset gpio\n");
158		return;
159	}
160
161	sc->sc_clk_pcie = fdtbus_clock_get(phandle, "pcie");
162	if (sc->sc_clk_pcie == NULL) {
163		aprint_error(": couldn't get clock pcie_axi\n");
164		return;
165	}
166	sc->sc_clk_pcie_bus = fdtbus_clock_get(phandle, "pcie_bus");
167	if (sc->sc_clk_pcie_bus == NULL) {
168		aprint_error(": couldn't get clock lvds1_gate\n");
169		return;
170	}
171	sc->sc_clk_pcie_phy = fdtbus_clock_get(phandle, "pcie_phy");
172	if (sc->sc_clk_pcie_phy == NULL) {
173		aprint_error(": couldn't get clock pcie_ref\n");
174		return;
175	}
176
177	if (of_hasprop(phandle, "vpcie-supply")) {
178		ifsc->sc_reg_vpcie = fdtbus_regulator_acquire(phandle, "vpcie-supply");
179		if (ifsc->sc_reg_vpcie == NULL) {
180			aprint_error(": couldn't acquire regulator\n");
181			return;
182		}
183		aprint_normal_dev(self, "regulator On\n");
184		fdtbus_regulator_enable(ifsc->sc_reg_vpcie);
185	}
186
187	if (of_hasprop(phandle, "ext_osc")) {
188		aprint_normal_dev(self, "Use external OSC\n");
189		sc->sc_ext_osc = true;
190
191		sc->sc_clk_pcie_ext = fdtbus_clock_get(phandle, "pcie_ext");
192		if (sc->sc_clk_pcie_ext == NULL) {
193			aprint_error(": couldn't get clock pcie_ext\n");
194			return;
195		}
196		sc->sc_clk_pcie_ext_src = fdtbus_clock_get(phandle, "pcie_ext_src");
197		if (sc->sc_clk_pcie_ext_src == NULL) {
198			aprint_error(": couldn't get clock pcie_ext_src\n");
199			return;
200		}
201	} else {
202		sc->sc_ext_osc = false;
203		sc->sc_clk_pcie_ext = NULL;
204		sc->sc_clk_pcie_ext_src = NULL;
205	}
206
207	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
208		aprint_error_dev(self, "failed to decode interrupt\n");
209		return;
210	}
211
212	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
213	    FDT_INTR_MPSAFE, imxpcie_intr, sc, device_xname(self));
214	if (sc->sc_ih == NULL) {
215		aprint_error_dev(self, "failed to establish interrupt on %s\n",
216		    intrstr);
217		return;
218	}
219	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
220
221	imxpcie_attach_common(sc);
222}
223
224static void
225imx6_pcie_configure(void *cookie)
226{
227	struct imxpcie_fdt_softc * const ifsc = cookie;
228	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
229
230#ifdef PCI_NETBSD_CONFIGURE
231	struct pciconf_resources *pcires = pciconf_resource_init();
232
233	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
234	    IMX6_PCIE_IO_BASE, IMX6_PCIE_IO_SIZE);
235	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
236	    IMX6_PCIE_MEM_BASE, IMX6_PCIE_MEM_SIZE);
237
238	int error = pci_configure_bus(&sc->sc_pc, pcires, 0, arm_dcache_align);
239
240	pciconf_resource_fini(pcires);
241
242	if (error) {
243		aprint_error_dev(sc->sc_dev, "configuration failed (%d)\n",
244		    error);
245	}
246#endif
247}
248
249static uint32_t
250imx6_pcie_gpr_read(void *cookie, uint32_t reg)
251{
252	struct imxpcie_fdt_softc * const ifsc = cookie;
253	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
254	return bus_space_read_4(sc->sc_iot, sc->sc_gpr_ioh, reg);
255}
256
257static void
258imx6_pcie_gpr_write(void *cookie, uint32_t reg, uint32_t val)
259{
260	struct imxpcie_fdt_softc * const ifsc = cookie;
261	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
262	bus_space_write_4(sc->sc_iot, sc->sc_gpr_ioh, reg, val);
263}
264
265static void
266imx6_pcie_reset(void *cookie)
267{
268	struct imxpcie_fdt_softc * const ifsc = cookie;
269
270	fdtbus_gpio_write(ifsc->sc_pin_reset, 1);
271	delay(20 * 1000);
272	fdtbus_gpio_write(ifsc->sc_pin_reset, 0);
273}
274