tegra_var.h revision 1.34
1/* $NetBSD: tegra_var.h,v 1.34 2017/05/25 23:12:59 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef _ARM_TEGRA_VAR_H 30#define _ARM_TEGRA_VAR_H 31 32#include <sys/types.h> 33#include <sys/bus.h> 34#include <sys/gpio.h> 35 36#include "opt_tegra.h" 37 38extern struct bus_space armv7_generic_bs_tag; 39extern struct bus_space armv7_generic_a4x_bs_tag; 40extern bus_space_handle_t tegra_ppsb_bsh; 41extern bus_space_handle_t tegra_apb_bsh; 42extern struct arm32_bus_dma_tag tegra_dma_tag; 43 44#define CHIP_ID_TEGRA20 0x20 45#define CHIP_ID_TEGRA30 0x30 46#define CHIP_ID_TEGRA114 0x35 47#define CHIP_ID_TEGRA124 0x40 48#define CHIP_ID_TEGRA132 0x13 49#define CHIP_ID_TEGRA210 0x21 50 51u_int tegra_chip_id(void); 52const char *tegra_chip_name(void); 53void tegra_bootstrap(void); 54void tegra_dma_bootstrap(psize_t); 55 56struct tegra_gpio_pin; 57struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int); 58void tegra_gpio_release(struct tegra_gpio_pin *); 59int tegra_gpio_read(struct tegra_gpio_pin *); 60void tegra_gpio_write(struct tegra_gpio_pin *, int); 61 62struct tegra_mpio_padctlgrp { 63 int preemp; 64 int hsm; 65 int schmt; 66 int drv_type; 67 int drvdn; 68 int drvup; 69 int slwr; 70 int slwf; 71}; 72void tegra_mpio_padctlgrp_read(u_int, struct tegra_mpio_padctlgrp *); 73void tegra_mpio_padctlgrp_write(u_int, const struct tegra_mpio_padctlgrp *); 74 75void tegra_mpio_pinmux_set_config(u_int, int, const char *); 76void tegra_mpio_pinmux_set_io_reset(u_int, bool); 77void tegra_mpio_pinmux_set_rcv_sel(u_int, bool); 78void tegra_mpio_pinmux_get_config(u_int, int *, const char **); 79const char *tegra_mpio_pinmux_get_pm(u_int); 80bool tegra_mpio_pinmux_get_io_reset(u_int); 81bool tegra_mpio_pinmux_get_rcv_sel(u_int); 82 83void tegra_pmc_reset(void); 84void tegra_pmc_power(u_int, bool); 85void tegra_pmc_remove_clamping(u_int); 86void tegra_pmc_hdmi_enable(void); 87 88uint32_t tegra_fuse_read(u_int); 89 90void tegra_xusbpad_sata_enable(void); 91void tegra_xusbpad_xhci_enable(void); 92 93struct videomode; 94int tegra_dc_port(device_t); 95int tegra_dc_enable(device_t, device_t, const struct videomode *, 96 const uint8_t *); 97void tegra_dc_hdmi_start(device_t); 98 99#define TEGRA_CPUFREQ_MAX 16 100struct tegra_cpufreq_func { 101 u_int (*set_rate)(u_int); 102 u_int (*get_rate)(void); 103 size_t (*get_available)(u_int *, size_t); 104}; 105void tegra_cpufreq_register(const struct tegra_cpufreq_func *); 106 107#if defined(SOC_TEGRA124) 108void tegra124_mpinit(void); 109#endif 110 111static void inline 112tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh, 113 bus_size_t o, uint32_t set_mask, uint32_t clr_mask) 114{ 115 const uint32_t old = bus_space_read_4(bst, bsh, o); 116 const uint32_t new = set_mask | (old & ~clr_mask); 117 if (old != new) { 118 bus_space_write_4(bst, bsh, o, new); 119 } 120} 121 122#endif /* _ARM_TEGRA_VAR_H */ 123