tegra_var.h revision 1.31 
1/* $NetBSD: tegra_var.h,v 1.31 2017/04/14 00:19:34 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _ARM_TEGRA_VAR_H
30#define _ARM_TEGRA_VAR_H
31
32#include <sys/types.h>
33#include <sys/bus.h>
34#include <sys/gpio.h>
35
36#include "opt_tegra.h"
37
38extern struct bus_space armv7_generic_bs_tag;
39extern struct bus_space armv7_generic_a4x_bs_tag;
40extern bus_space_handle_t tegra_ppsb_bsh;
41extern bus_space_handle_t tegra_apb_bsh;
42extern struct arm32_bus_dma_tag tegra_dma_tag;
43
44#define CHIP_ID_TEGRA20		0x20
45#define CHIP_ID_TEGRA30		0x30
46#define CHIP_ID_TEGRA114	0x35
47#define CHIP_ID_TEGRA124	0x40
48#define CHIP_ID_TEGRA132	0x13
49
50u_int	tegra_chip_id(void);
51const char *tegra_chip_name(void);
52void	tegra_bootstrap(void);
53void	tegra_dma_bootstrap(psize_t);
54void	tegra_cpuinit(void);
55
56struct tegra_gpio_pin;
57struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
58void	tegra_gpio_release(struct tegra_gpio_pin *);
59int	tegra_gpio_read(struct tegra_gpio_pin *);
60void	tegra_gpio_write(struct tegra_gpio_pin *, int);
61
62struct tegra_mpio_padctlgrp {
63	int	preemp;
64	int	hsm;
65	int	schmt;
66	int	drv_type;
67	int	drvdn;
68	int	drvup;
69	int	slwr;
70	int	slwf;
71};
72void	tegra_mpio_padctlgrp_read(u_int, struct tegra_mpio_padctlgrp *);
73void	tegra_mpio_padctlgrp_write(u_int, const struct tegra_mpio_padctlgrp *);
74
75void	tegra_mpio_pinmux_set_config(u_int, int, const char *);
76void	tegra_mpio_pinmux_set_io_reset(u_int, bool);
77void	tegra_mpio_pinmux_set_rcv_sel(u_int, bool);
78void	tegra_mpio_pinmux_get_config(u_int, int *, const char **);
79const char *tegra_mpio_pinmux_get_pm(u_int);
80bool	tegra_mpio_pinmux_get_io_reset(u_int);
81bool	tegra_mpio_pinmux_get_rcv_sel(u_int);
82
83void	tegra_pmc_reset(void);
84void	tegra_pmc_power(u_int, bool);
85void	tegra_pmc_remove_clamping(u_int);
86void	tegra_pmc_hdmi_enable(void);
87
88psize_t	tegra_mc_memsize(void);
89
90uint32_t tegra_fuse_read(u_int);
91
92void	tegra_xusbpad_sata_enable(void);
93void	tegra_xusbpad_xhci_enable(void);
94
95struct videomode;
96int	tegra_dc_port(device_t);
97int	tegra_dc_enable(device_t, device_t, const struct videomode *,
98			const uint8_t *);
99void	tegra_dc_hdmi_start(device_t);
100
101#define TEGRA_CPUFREQ_MAX	16
102struct tegra_cpufreq_func {
103	u_int (*set_rate)(u_int);
104	u_int (*get_rate)(void);
105	size_t (*get_available)(u_int *, size_t);
106};
107void	tegra_cpufreq_register(const struct tegra_cpufreq_func *);
108void	tegra_cpufreq_init(void);
109
110#if defined(SOC_TEGRA124)
111void	tegra124_cpuinit(void);
112void	tegra124_mpinit(void);
113#endif
114
115static void inline
116tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
117    bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
118{
119	const uint32_t old = bus_space_read_4(bst, bsh, o);
120	const uint32_t new = set_mask | (old & ~clr_mask);
121	if (old != new) {
122		bus_space_write_4(bst, bsh, o, new);
123	}
124}
125
126#endif /* _ARM_TEGRA_VAR_H */
127