tegra_var.h revision 1.17
1/* $NetBSD: tegra_var.h,v 1.17 2015/05/18 19:32:48 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef _ARM_TEGRA_VAR_H 30#define _ARM_TEGRA_VAR_H 31 32#include <sys/types.h> 33#include <sys/bus.h> 34#include <sys/gpio.h> 35 36#include "opt_tegra.h" 37 38struct tegra_locators { 39 const char *loc_name; 40 bus_addr_t loc_offset; 41 bus_size_t loc_size; 42 int loc_port; 43 int loc_intr; 44#define TEGRAIO_INTR_DEFAULT 0 45}; 46 47struct tegraio_attach_args { 48 struct tegra_locators tio_loc; 49 bus_space_tag_t tio_bst; 50 bus_space_tag_t tio_a4x_bst; 51 bus_space_handle_t tio_bsh; 52 bus_dma_tag_t tio_dmat; 53 bus_dma_tag_t tio_coherent_dmat; 54}; 55 56struct tegrafb_attach_args { 57 bool tfb_console; 58 bus_dma_tag_t tfb_dmat; 59 bus_dmamap_t tfb_dmamap; 60 void *tfb_dmap; 61 u_int tfb_width; 62 u_int tfb_height; 63 u_int tfb_depth; 64 u_int tfb_stride; 65 device_t tfb_outputdev; 66}; 67 68extern struct bus_space armv7_generic_bs_tag; 69extern struct bus_space armv7_generic_a4x_bs_tag; 70extern bus_space_handle_t tegra_host1x_bsh; 71extern bus_space_handle_t tegra_ppsb_bsh; 72extern bus_space_handle_t tegra_apb_bsh; 73extern bus_space_handle_t tegra_ahb_a2_bsh; 74extern struct arm32_bus_dma_tag tegra_dma_tag; 75extern struct arm32_bus_dma_tag tegra_coherent_dma_tag; 76 77#define CHIP_ID_TEGRA20 0x20 78#define CHIP_ID_TEGRA30 0x30 79#define CHIP_ID_TEGRA114 0x35 80#define CHIP_ID_TEGRA124 0x40 81#define CHIP_ID_TEGRA132 0x13 82 83u_int tegra_chip_id(void); 84const char *tegra_chip_name(void); 85void tegra_bootstrap(void); 86void tegra_dma_bootstrap(psize_t); 87void tegra_cpuinit(void); 88 89u_int tegra_car_osc_rate(void); 90u_int tegra_car_pllc_rate(void); 91u_int tegra_car_plle_rate(void); 92u_int tegra_car_pllx_rate(void); 93void tegra_car_pllx_set_rate(u_int, u_int, u_int); 94u_int tegra_car_pllu_rate(void); 95u_int tegra_car_pllp0_rate(void); 96u_int tegra_car_plld2_rate(void); 97u_int tegra_car_uart_rate(u_int); 98u_int tegra_car_periph_sdmmc_rate(u_int); 99int tegra_car_periph_sdmmc_set_div(u_int, u_int); 100int tegra_car_periph_usb_enable(u_int); 101void tegra_car_periph_hda_enable(void); 102void tegra_car_periph_sata_enable(void); 103int tegra_car_periph_i2c_enable(u_int, u_int); 104void tegra_car_utmip_init(void); 105void tegra_car_utmip_enable(u_int); 106void tegra_car_hdmi_enable(u_int); 107int tegra_car_dc_enable(u_int); 108 109struct tegra_gpio_pin; 110struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int); 111void tegra_gpio_release(struct tegra_gpio_pin *); 112int tegra_gpio_read(struct tegra_gpio_pin *); 113void tegra_gpio_write(struct tegra_gpio_pin *, int); 114 115struct tegra_mpio_padctlgrp { 116 int preemp; 117 int hsm; 118 int schmt; 119 int drv_type; 120 int drvdn; 121 int drvup; 122 int slwr; 123 int slwf; 124}; 125void tegra_mpio_padctlgrp_read(u_int, struct tegra_mpio_padctlgrp *); 126void tegra_mpio_padctlgrp_write(u_int, const struct tegra_mpio_padctlgrp *); 127 128void tegra_mpio_pinmux_set_config(u_int, int, const char *); 129void tegra_mpio_pinmux_set_io_reset(u_int, bool); 130void tegra_mpio_pinmux_set_rcv_sel(u_int, bool); 131void tegra_mpio_pinmux_get_config(u_int, int *, const char **); 132const char *tegra_mpio_pinmux_get_pm(u_int); 133bool tegra_mpio_pinmux_get_io_reset(u_int); 134bool tegra_mpio_pinmux_get_rcv_sel(u_int); 135 136void tegra_pmc_reset(void); 137void tegra_pmc_power(u_int, bool); 138void tegra_pmc_remove_clamping(u_int); 139 140psize_t tegra_mc_memsize(void); 141 142void tegra_xusbpad_sata_enable(void); 143 144struct videomode; 145int tegra_dc_port(device_t); 146int tegra_dc_enable(device_t, device_t, const struct videomode *); 147void tegra_dc_hdmi_start(device_t); 148 149#define TEGRA_CPUFREQ_MAX 16 150struct tegra_cpufreq_func { 151 u_int (*set_rate)(u_int); 152 u_int (*get_rate)(void); 153 size_t (*get_available)(u_int *, size_t); 154}; 155void tegra_cpufreq_register(const struct tegra_cpufreq_func *); 156void tegra_cpufreq_init(void); 157 158#if defined(SOC_TEGRA124) 159void tegra124_cpuinit(void); 160void tegra124_mpinit(void); 161#endif 162 163static void inline 164tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh, 165 bus_size_t o, uint32_t set_mask, uint32_t clr_mask) 166{ 167 const uint32_t old = bus_space_read_4(bst, bsh, o); 168 const uint32_t new = set_mask | (old & ~clr_mask); 169 if (old != new) { 170 bus_space_write_4(bst, bsh, o, new); 171 } 172} 173 174#endif /* _ARM_TEGRA_VAR_H */ 175