tegra_pmc.c revision 1.8 
1/* $NetBSD: tegra_pmc.c,v 1.8 2015/12/13 17:39:19 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.8 2015/12/13 17:39:19 jmcneill Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38
39#include <arm/nvidia/tegra_reg.h>
40#include <arm/nvidia/tegra_pmcreg.h>
41#include <arm/nvidia/tegra_var.h>
42
43#include <dev/fdt/fdtvar.h>
44
45static int	tegra_pmc_match(device_t, cfdata_t, void *);
46static void	tegra_pmc_attach(device_t, device_t, void *);
47
48struct tegra_pmc_softc {
49	device_t		sc_dev;
50	bus_space_tag_t		sc_bst;
51	bus_space_handle_t	sc_bsh;
52};
53
54static struct tegra_pmc_softc *pmc_softc = NULL;
55
56CFATTACH_DECL_NEW(tegra_pmc, sizeof(struct tegra_pmc_softc),
57	tegra_pmc_match, tegra_pmc_attach, NULL, NULL);
58
59static int
60tegra_pmc_match(device_t parent, cfdata_t cf, void *aux)
61{
62	const char * const compatible[] = { "nvidia,tegra124-pmc", NULL };
63	struct fdt_attach_args * const faa = aux;
64
65	return of_match_compatible(faa->faa_phandle, compatible);
66}
67
68static void
69tegra_pmc_attach(device_t parent, device_t self, void *aux)
70{
71	struct tegra_pmc_softc * const sc = device_private(self);
72	struct fdt_attach_args * const faa = aux;
73	bus_addr_t addr;
74	bus_size_t size;
75	int error;
76
77	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
78		aprint_error(": couldn't get registers\n");
79		return;
80	}
81
82	sc->sc_dev = self;
83	sc->sc_bst = faa->faa_bst;
84	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
85	if (error) {
86		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
87		return;
88	}
89
90	KASSERT(pmc_softc == NULL);
91	pmc_softc = sc;
92
93	aprint_naive("\n");
94	aprint_normal(": PMC\n");
95}
96
97static void
98tegra_pmc_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
99{
100	if (pmc_softc) {
101		*pbst = pmc_softc->sc_bst;
102		*pbsh = pmc_softc->sc_bsh;
103	} else {
104		*pbst = &armv7_generic_bs_tag;
105		bus_space_subregion(*pbst, tegra_apb_bsh,
106		    TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, pbsh);
107	}
108}
109
110void
111tegra_pmc_reset(void)
112{
113	bus_space_tag_t bst;
114	bus_space_handle_t bsh;
115	uint32_t cntrl;
116
117	tegra_pmc_get_bs(&bst, &bsh);
118
119	cntrl = bus_space_read_4(bst, bsh, PMC_CNTRL_0_REG);
120	cntrl |= PMC_CNTRL_0_MAIN_RST;
121	bus_space_write_4(bst, bsh, PMC_CNTRL_0_REG, cntrl);
122
123	for (;;) {
124		__asm("wfi");
125	}
126}
127
128void
129tegra_pmc_power(u_int partid, bool enable)
130{
131	bus_space_tag_t bst;
132	bus_space_handle_t bsh;
133	uint32_t status, toggle;
134	bool state;
135	int retry = 10000;
136
137	tegra_pmc_get_bs(&bst, &bsh);
138
139	status = bus_space_read_4(bst, bsh, PMC_PWRGATE_STATUS_0_REG);
140	state = !!(status & __BIT(partid));
141	if (state == enable)
142		return;
143
144	while (--retry > 0) {
145		toggle = bus_space_read_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG);
146		if ((toggle & PMC_PWRGATE_TOGGLE_0_START) == 0)
147			break;
148		delay(1);
149	}
150	if (retry == 0) {
151		printf("ERROR: Couldn't enable PMC partition %#x\n", partid);
152		return;
153	}
154
155	bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG,
156	    __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) |
157	    PMC_PWRGATE_TOGGLE_0_START);
158}
159
160void
161tegra_pmc_remove_clamping(u_int partid)
162{
163	bus_space_tag_t bst;
164	bus_space_handle_t bsh;
165
166	tegra_pmc_get_bs(&bst, &bsh);
167
168	if (tegra_chip_id() == CHIP_ID_TEGRA124) {
169		/*
170		 * On Tegra124 the GPU power clamping is controlled by a
171		 * separate register
172		 */
173		bus_space_write_4(bst, bsh, PMC_GPU_RG_CNTRL_REG, 0);
174		return;
175	}
176
177	bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG,
178	    __BIT(partid));
179}
180
181void
182tegra_pmc_hdmi_enable(void)
183{
184	bus_space_tag_t bst;
185	bus_space_handle_t bsh;
186
187	tegra_pmc_get_bs(&bst, &bsh);
188
189	tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG,
190	    0, PMC_IO_DPD_STATUS_HDMI);
191	tegra_reg_set_clear(bst, bsh, PMC_IO_DPD2_STATUS_REG,
192	    0, PMC_IO_DPD2_STATUS_HV);
193}
194