tegra_pmc.c revision 1.12 
1/* $NetBSD: tegra_pmc.c,v 1.12 2018/04/01 04:35:04 ryo Exp $ */
2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: tegra_pmc.c,v 1.12 2018/04/01 04:35:04 ryo Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38
39#include <arm/nvidia/tegra_reg.h>
40#include <arm/nvidia/tegra_pmcreg.h>
41#include <arm/nvidia/tegra_var.h>
42
43#include <dev/fdt/fdtvar.h>
44
45static int	tegra_pmc_match(device_t, cfdata_t, void *);
46static void	tegra_pmc_attach(device_t, device_t, void *);
47
48struct tegra_pmc_softc {
49	device_t		sc_dev;
50	bus_space_tag_t		sc_bst;
51	bus_space_handle_t	sc_bsh;
52};
53
54static struct tegra_pmc_softc *pmc_softc = NULL;
55
56CFATTACH_DECL_NEW(tegra_pmc, sizeof(struct tegra_pmc_softc),
57	tegra_pmc_match, tegra_pmc_attach, NULL, NULL);
58
59static int
60tegra_pmc_match(device_t parent, cfdata_t cf, void *aux)
61{
62	const char * const compatible[] = {
63		"nvidia,tegra210-pmc",
64		"nvidia,tegra124-pmc",
65		NULL
66	};
67	struct fdt_attach_args * const faa = aux;
68
69	return of_match_compatible(faa->faa_phandle, compatible);
70}
71
72static void
73tegra_pmc_attach(device_t parent, device_t self, void *aux)
74{
75	struct tegra_pmc_softc * const sc = device_private(self);
76	struct fdt_attach_args * const faa = aux;
77	bus_addr_t addr;
78	bus_size_t size;
79	int error;
80
81	if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
82		aprint_error(": couldn't get registers\n");
83		return;
84	}
85
86	sc->sc_dev = self;
87	sc->sc_bst = faa->faa_bst;
88	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
89	if (error) {
90		aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
91		return;
92	}
93
94	KASSERT(pmc_softc == NULL);
95	pmc_softc = sc;
96
97	aprint_naive("\n");
98	aprint_normal(": PMC\n");
99}
100
101static void
102tegra_pmc_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
103{
104	if (pmc_softc) {
105		*pbst = pmc_softc->sc_bst;
106		*pbsh = pmc_softc->sc_bsh;
107	} else {
108		extern struct bus_space arm_generic_bs_tag;
109
110		*pbst = &arm_generic_bs_tag;
111
112		bus_space_subregion(*pbst, tegra_apb_bsh,
113		    TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, pbsh);
114	}
115}
116
117void
118tegra_pmc_reset(void)
119{
120	bus_space_tag_t bst;
121	bus_space_handle_t bsh;
122	uint32_t cntrl;
123
124	tegra_pmc_get_bs(&bst, &bsh);
125
126	cntrl = bus_space_read_4(bst, bsh, PMC_CNTRL_0_REG);
127	cntrl |= PMC_CNTRL_0_MAIN_RST;
128	bus_space_write_4(bst, bsh, PMC_CNTRL_0_REG, cntrl);
129
130	for (;;) {
131		__asm("wfi");
132	}
133}
134
135void
136tegra_pmc_power(u_int partid, bool enable)
137{
138	bus_space_tag_t bst;
139	bus_space_handle_t bsh;
140	uint32_t status, toggle;
141	bool state;
142	int retry = 10000;
143
144	tegra_pmc_get_bs(&bst, &bsh);
145
146	status = bus_space_read_4(bst, bsh, PMC_PWRGATE_STATUS_0_REG);
147	state = !!(status & __BIT(partid));
148	if (state == enable)
149		return;
150
151	while (--retry > 0) {
152		toggle = bus_space_read_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG);
153		if ((toggle & PMC_PWRGATE_TOGGLE_0_START) == 0)
154			break;
155		delay(1);
156	}
157	if (retry == 0) {
158		printf("ERROR: Couldn't enable PMC partition %#x\n", partid);
159		return;
160	}
161
162	bus_space_write_4(bst, bsh, PMC_PWRGATE_TOGGLE_0_REG,
163	    __SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) |
164	    PMC_PWRGATE_TOGGLE_0_START);
165}
166
167void
168tegra_pmc_remove_clamping(u_int partid)
169{
170	bus_space_tag_t bst;
171	bus_space_handle_t bsh;
172
173	tegra_pmc_get_bs(&bst, &bsh);
174
175	if (partid == PMC_PARTID_TD) {
176		/*
177		 * On Tegra124 and later, the GPU power clamping is
178		 * controlled by a separate register
179		 */
180		bus_space_write_4(bst, bsh, PMC_GPU_RG_CNTRL_REG, 0);
181		return;
182	}
183
184	bus_space_write_4(bst, bsh, PMC_REMOVE_CLAMPING_CMD_0_REG,
185	    __BIT(partid));
186}
187
188void
189tegra_pmc_hdmi_enable(void)
190{
191	bus_space_tag_t bst;
192	bus_space_handle_t bsh;
193
194	tegra_pmc_get_bs(&bst, &bsh);
195
196	tegra_reg_set_clear(bst, bsh, PMC_IO_DPD_STATUS_REG,
197	    0, PMC_IO_DPD_STATUS_HDMI);
198	tegra_reg_set_clear(bst, bsh, PMC_IO_DPD2_STATUS_REG,
199	    0, PMC_IO_DPD2_STATUS_HV);
200}
201