1/* $NetBSD: cputypes.h,v 1.16 2021/11/13 01:09:51 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39#ifndef _ARM_CPUTYPES_H_ 40#define _ARM_CPUTYPES_H_ 41 42/* 43 * The CPU ID register is theoretically structured, but the definitions of 44 * the fields keep changing. 45 */ 46 47/* The high-order byte is always the implementor */ 48#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 49#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 50#define CPU_ID_BROADCOM 0x42000000 /* 'B' */ 51#define CPU_ID_CAVIUM 0x43000000 /* 'C' */ 52#define CPU_ID_DEC 0x44000000 /* 'D' */ 53#define CPU_ID_INFINEON 0x49000000 /* 'I' */ 54#define CPU_ID_MOTOROLA 0x4d000000 /* 'M' */ 55#define CPU_ID_NVIDIA 0x4e000000 /* 'N' */ 56#define CPU_ID_APM 0x50000000 /* 'P' */ 57#define CPU_ID_QUALCOMM 0x51000000 /* 'Q' */ 58#define CPU_ID_SAMSUNG 0x53000000 /* 'S' */ 59#define CPU_ID_TI 0x54000000 /* 'T' */ 60#define CPU_ID_MARVELL 0x56000000 /* 'V' */ 61#define CPU_ID_APPLE 0x61000000 /* 'a' */ 62#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 63#define CPU_ID_INTEL 0x69000000 /* 'i' */ 64 65/* How to decide what format the CPUID is in. */ 66#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 67#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 68#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 69 70/* On ARM3 and ARM6, this byte holds the foundry ID. */ 71#define CPU_ID_FOUNDRY_MASK 0x00ff0000 72#define CPU_ID_FOUNDRY_VLSI 0x00560000 73 74/* On ARM7 it holds the architecture and variant (sub-model) */ 75#define CPU_ID_7ARCH_MASK 0x00800000 76#define CPU_ID_7ARCH_V3 0x00000000 77#define CPU_ID_7ARCH_V4T 0x00800000 78#define CPU_ID_7VARIANT_MASK 0x007f0000 79 80/* On more recent ARMs, it does the same, but in a different format */ 81#define CPU_ID_ARCH_MASK 0x000f0000 82#define CPU_ID_ARCH_V3 0x00000000 83#define CPU_ID_ARCH_V4 0x00010000 84#define CPU_ID_ARCH_V4T 0x00020000 85#define CPU_ID_ARCH_V5 0x00030000 86#define CPU_ID_ARCH_V5T 0x00040000 87#define CPU_ID_ARCH_V5TE 0x00050000 88#define CPU_ID_ARCH_V5TEJ 0x00060000 89#define CPU_ID_ARCH_V6 0x00070000 90#define CPU_ID_VARIANT_MASK 0x00f00000 91 92/* Next three nybbles are part number */ 93#define CPU_ID_PARTNO_MASK 0x0000fff0 94 95/* Intel XScale has sub fields in part number */ 96#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 97#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 98#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 99 100/* And finally, the revision number. */ 101#define CPU_ID_REVISION_MASK 0x0000000f 102 103/* Individual CPUs are probably best IDed by everything but the revision. */ 104#define CPU_ID_CPU_MASK 0xfffffff0 105 106/* Fake CPU IDs for ARMs without CP15 */ 107#define CPU_ID_ARM2 0x41560200 108#define CPU_ID_ARM250 0x41560250 109 110/* Pre-ARM7 CPUs -- [15:12] == 0 */ 111#define CPU_ID_ARM3 0x41560300 112#define CPU_ID_ARM600 0x41560600 113#define CPU_ID_ARM610 0x41560610 114#define CPU_ID_ARM620 0x41560620 115 116/* ARM7 CPUs -- [15:12] == 7 */ 117#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 118#define CPU_ID_ARM710 0x41007100 119#define CPU_ID_ARM7500 0x41027100 120#define CPU_ID_ARM710A 0x41067100 121#define CPU_ID_ARM7500FE 0x41077100 122#define CPU_ID_ARM710T 0x41807100 123#define CPU_ID_ARM720T 0x41807200 124#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 125#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 126 127/* Post-ARM7 CPUs */ 128#define CPU_ID_ARM810 0x41018100 129#define CPU_ID_ARM920T 0x41129200 130#define CPU_ID_ARM922T 0x41029220 131#define CPU_ID_ARM926EJS 0x41069260 132#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 133#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 134#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 135#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 136#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 137#define CPU_ID_ARM1022ES 0x4105a220 138#define CPU_ID_ARM1026EJS 0x4106a260 139#define CPU_ID_ARM11MPCORE 0x410fb020 140#define CPU_ID_ARM1136JS 0x4107b360 141#define CPU_ID_ARM1136JSR1 0x4117b360 142#define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ 143#define CPU_ID_ARM1176JZS 0x410fb760 144#define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 145 146/* ARMv7 CPUs */ 147#define CPU_ID_CORTEXA5R0 0x410fc050 148#define CPU_ID_CORTEXA7R0 0x410fc070 149#define CPU_ID_CORTEXA8R1 0x411fc080 150#define CPU_ID_CORTEXA8R2 0x412fc080 151#define CPU_ID_CORTEXA8R3 0x413fc080 152#define CPU_ID_CORTEXA9R1 0x411fc090 153#define CPU_ID_CORTEXA9R2 0x412fc090 154#define CPU_ID_CORTEXA9R3 0x413fc090 155#define CPU_ID_CORTEXA9R4 0x414fc090 156#define CPU_ID_CORTEXA12R0 0x410fc0d0 157#define CPU_ID_CORTEXA15R2 0x412fc0f0 158#define CPU_ID_CORTEXA15R3 0x413fc0f0 159#define CPU_ID_CORTEXA15R4 0x414fc0f0 160#define CPU_ID_CORTEXA17R1 0x411fc0e0 161 162/* ARMv8 CPUS */ 163#define CPU_ID_CORTEXA32R1 0x411fd010 164#define CPU_ID_CORTEXA35R0 0x410fd040 165#define CPU_ID_CORTEXA35R1 0x411fd040 166#define CPU_ID_CORTEXA53R0 0x410fd030 167#define CPU_ID_CORTEXA55R1 0x411fd050 168#define CPU_ID_CORTEXA57R0 0x410fd070 169#define CPU_ID_CORTEXA57R1 0x411fd070 170#define CPU_ID_CORTEXA65R0 0x410fd060 171#define CPU_ID_CORTEXA72R0 0x410fd080 172#define CPU_ID_CORTEXA73R0 0x410fd090 173#define CPU_ID_CORTEXA75R2 0x412fd0a0 174#define CPU_ID_CORTEXA76AER1 0x411fd0e0 175#define CPU_ID_CORTEXA76R3 0x413fd0b0 176#define CPU_ID_NEOVERSEN1R3 0x413fd0c0 177#define CPU_ID_NEOVERSEE1R1 0x411fd4a0 178#define CPU_ID_CORTEXA77R0 0x410fd0d0 179 180#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) 181#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 182#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 183#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 184#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 185#define CPU_ID_CORTEX_A12_P(n) ((n & 0xff0ff0f0) == 0x410fc0d0) 186#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) 187#define CPU_ID_CORTEX_A17_P(n) ((n & 0xff0ff0f0) == 0x410fc0e0) 188#define CPU_ID_CORTEX_A32_P(n) ((n & 0xff0ff0f0) == 0x410fd010) 189#define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040) 190#define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030) 191#define CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050) 192#define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070) 193#define CPU_ID_CORTEX_A65_P(n) ((n & 0xff0ff0f0) == 0x410fd060) 194#define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080) 195#define CPU_ID_CORTEX_A73_P(n) ((n & 0xff0ff0f0) == 0x410fd090) 196#define CPU_ID_CORTEX_A75_P(n) ((n & 0xff0ff0f0) == 0x410fd0a0) 197#define CPU_ID_CORTEX_A76_P(n) ((n & 0xff0ff0f0) == 0x410fd0b0) 198#define CPU_ID_CORTEX_A76AE_P(n) ((n & 0xff0ff0f0) == 0x410fd0e0) 199#define CPU_ID_CORTEX_A77_P(n) ((n & 0xff0ff0f0) == 0x410fd0f0) 200 201#define CPU_ID_NEOVERSEN1_P(n) ((n & 0xff0ffff0) == 0x410fd0c0) 202 203#define CPU_ID_THUNDERXRX 0x43000a10 204#define CPU_ID_THUNDERXP1d0 0x43000a10 205#define CPU_ID_THUNDERXP1d1 0x43000a11 206#define CPU_ID_THUNDERXP2d1 0x431f0a11 207#define CPU_ID_THUNDERX81XXRX 0x43000a20 208#define CPU_ID_THUNDERX83XXRX 0x43000a30 209#define CPU_ID_THUNDERX2RX 0x43000af0 210 211/* 212 * Chip-specific errata. These defines are intended to be 213 * booleans used within if statements. When an appropriate 214 * kernel option is disabled, these defines must be defined 215 * as 0 to allow the compiler to remove a dead code thus 216 * produce better optimized kernel image. 217 */ 218/* 219 * Vendor: Cavium 220 * Chip: ThunderX 221 * Revision(s): Pass 1.0, Pass 1.1 222 */ 223#define CPU_ID_ERRATA_CAVIUM_THUNDERX_1_1_P(n) \ 224 (((n) & 0xfff0ffff) == CPU_ID_THUNDERXP1d0 || \ 225 ((n) & 0xfff0ffff) == CPU_ID_THUNDERXP1d1) 226 227#define CPU_ID_APPLE_M1_ICESTORM 0x61000220 228#define CPU_ID_APPLE_M1_FIRESTORM 0x61000230 229 230#define CPU_ID_SA110 0x4401a100 231#define CPU_ID_SA1100 0x4401a110 232#define CPU_ID_NVIDIADENVER2 0x4e0f0030 233#define CPU_ID_EMAG8180 0x503f0002 234#define CPU_ID_TI925T 0x54029250 235#define CPU_ID_MV88FR571_VD 0x56155710 236#define CPU_ID_MV88SV131 0x56251310 237#define CPU_ID_FA526 0x66015260 238#define CPU_ID_SA1110 0x6901b110 239#define CPU_ID_IXP1200 0x6901c120 240#define CPU_ID_80200 0x69052000 241#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 242#define CPU_ID_PXA210 0x69052120 243#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 244#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 245#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 246#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 247#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 248#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 249#define CPU_ID_PXA27X 0x69054110 250#define CPU_ID_80321_400 0x69052420 251#define CPU_ID_80321_600 0x69052430 252#define CPU_ID_80321_400_B0 0x69052c20 253#define CPU_ID_80321_600_B0 0x69052c30 254#define CPU_ID_80219_400 0x69052e20 255#define CPU_ID_80219_600 0x69052e30 256#define CPU_ID_IXP425_533 0x690541c0 257#define CPU_ID_IXP425_400 0x690541d0 258#define CPU_ID_IXP425_266 0x690541f0 259#define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) 260#define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ 261#define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ 262#define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ 263#define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ 264/* Marvell's CPUIDs with ARM ID in implementor field */ 265#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 266#define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ 267#define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ 268 269#endif /* _ARM_CPUTYPES_H_ */ 270