1/* $NetBSD: imx31_intrreg.h,v 1.2 2008/04/27 18:58:44 matt Exp $ */ 2/*- 3 * Copyright (c) 2007 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#ifndef _ARM_IMX_IMX31_INTRREG_H_ 31#define _ARM_IMX_IMX31_INTRREG_H_ 32 33#define IMX31_INTC_BASE 0x68000000 34#define IMX31_INTCNTL 0x0000 /* Interrupt Control (RW) */ 35#define IMX31_NIMASK 0x0004 /* Normal Interrupt Mask (RW) */ 36#define IMX31_INTENNUM 0x0008 /* Interrupt Enable Number (RW) */ 37#define IMX31_INTDISNUM 0x000c /* Interrupt Disable Number (RW) */ 38#define IMX31_INTENABLEH 0x0010 /* Interrupt Enable High (RW) */ 39#define IMX31_INTENABLEL 0x0014 /* Interrupt Enable Low (RW) */ 40#define IMX31_INTTYPEH 0x0018 /* Interrupt Type High (RW) */ 41#define IMX31_INTTYPEL 0x001c /* Interrupt Type Low (RW) */ 42#define IMX31_NIPRIORITY7 0x0020 /* Normal Intr Priority Level 7 (RW) */ 43#define IMX31_NIPRIORITY6 0x0024 /* Normal Intr Priority Level 6 (RW) */ 44#define IMX31_NIPRIORITY5 0x0028 /* Normal Intr Priority Level 5 (RW) */ 45#define IMX31_NIPRIORITY4 0x002c /* Normal Intr Priority Level 4 (RW) */ 46#define IMX31_NIPRIORITY3 0x0030 /* Normal Intr Priority Level 3 (RW) */ 47#define IMX31_NIPRIORITY2 0x0034 /* Normal Intr Priority Level 2 (RW) */ 48#define IMX31_NIPRIORITY1 0x0038 /* Normal Intr Priority Level 1 (RW) */ 49#define IMX31_NIPRIORITY0 0x003c /* Normal Intr Priority Level 0 (RW) */ 50#define IMX31_NIVECSR 0x0040 /* Normal Interrupt Vector Status (R) */ 51#define IMX31_FIVECSR 0x0044 /* Fast Interrupt Vector Status (R) */ 52#define IMX31_INTSRCH 0x0048 /* Interrupt Source High (R) */ 53#define IMX31_INTSRCL 0x004c /* Interrupt Source Low (R) */ 54#define IMX31_INTFRCH 0x0050 /* Interrupt Force High (RW) */ 55#define IMX31_INTFRCL 0x0054 /* Interrupt Force Low (RW) */ 56#define IMX31_NIPNDH 0x0058 /* Normal Intr Pending High (R) */ 57#define IMX31_NIPNDL 0x005c /* Normal Intr Pending Low (R) */ 58#define IMX31_FIPNDH 0x0060 /* Fast Intr Pending High (R) */ 59#define IMX31_FIPNDL 0x0064 /* Fast Intr Pending Low (R) */ 60 61#define IMX31_VECTOR(n) (0x0100 + (n) * 4) /* Vector [N] */ 62 63#define INTCNTL_ABFLAG (1 << 25) /* Core Arb. Priorty Risen (W1C) */ 64#define INTCNTL_ABFEN (1 << 24) /* ABFLAG Sticky Enable */ 65#define INTCNTL_NIDIS (1 << 22) /* Normal Intr. Disable */ 66#define INTCNTL_FIDIS (1 << 21) /* Fast Intr. Disable */ 67#define INTCNTL_NIAD (1 << 20) /* Normal Intr. Arbiter Rise ARM Lvl */ 68#define INTCNTL_FIAD (1 << 19) /* Fast Intr. Arbiter Rise ARM Level */ 69#define INTCNTL_NM (1 << 18) /* Normal Intr. Mode Control (1=AVIC) */ 70 71#define NIMASK_DIS_NONE -1 72 73/* 74 * INTTYPE (0 = IRQ, 1 = FIQ) 75 */ 76#endif /* _ARM_IMX_IMX31_INTRREG_H_ */ 77