1/* $Id: imx23_emireg.h,v 1.1 2012/11/20 19:06:13 jkunz Exp $ */ 2 3/* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ARM_IMX_IMX23_EMIREG_H_ 33#define _ARM_IMX_IMX23_EMIREG_H_ 34 35#include <sys/cdefs.h> 36 37#define HW_EMI_CTRL_BASE 0x80020000 38#define HW_DRAM_BASE 0x800E0000 39 40/* 41 * EMI Control Register. 42 */ 43#define HW_EMI_CTRL 0x000 44#define HW_EMI_CTRL_SET 0x004 45#define HW_EMI_CTRL_CLR 0x008 46#define HW_EMI_CTRL_TOG 0x00C 47 48#define HW_EMI_CTRL_SFTRST __BIT(31) 49#define HW_EMI_CTRL_RSVD6 __BIT(30) 50#define HW_EMI_CTRL_TRAP_SR __BIT(29) 51#define HW_EMI_CTRL_TRAP_INIT __BIT(28) 52#define HW_EMI_CTRL_AXI_DEPTH __BITS(27, 26) 53#define HW_EMI_CTRL_DLL_SHIFT_RESET __BIT(25) 54#define HW_EMI_CTRL_DLL_RESET __BIT(24) 55#define HW_EMI_CTRL_ARB_MODE __BITS(23, 22) 56#define HW_EMI_CTRL_RSVD5 __BIT(21) 57#define HW_EMI_CTRL_PORT_PRIORITY_ORDER __BITS(20, 16) 58#define HW_EMI_CTRL_RSVD4 __BIT(15) 59#define HW_EMI_CTRL_PRIORITY_WRITE_ITER __BITS(14, 12) 60#define HW_EMI_CTRL_RSVD3 __BIT(11) 61#define HW_EMI_CTRL_HIGH_PRIORITY_WRITE __BITS(10, 8) 62#define HW_EMI_CTRL_RSVD2 __BIT(7) 63#define HW_EMI_CTRL_MEM_WIDTH __BIT(6) 64#define HW_EMI_CTRL_RSVD1 __BIT(5) 65#define HW_EMI_CTRL_RESET_OUT __BIT(4) 66#define HW_EMI_CTRL_RSVD0 __BITS(3, 0) 67 68/* 69 * EMI Version Register. 70 */ 71#define HW_EMI_VERSION 0x0F0 72 73#define HW_EMI_VERSION_MAJOR __BITS(31, 24) 74#define HW_EMI_VERSION_MINOR __BITS(23, 16) 75#define HW_EMI_VERSION_STEP __BITS(15, 0) 76 77/* 78 * DRAM Control Register 0. 79 */ 80#define HW_DRAM_CTL00 0x000 81 82#define HW_DRAM_CTL00_RSVD4 __BITS(31, 25) 83#define HW_DRAM_CTL00_AHB0_W_PRIORITY __BIT(24) 84#define HW_DRAM_CTL00_RSVD3 __BITS(23, 17) 85#define HW_DRAM_CTL00_AHB0_R_PRIORITY __BIT(16) 86#define HW_DRAM_CTL00_RSVD2 __BITS(15, 9) 87#define HW_DRAM_CTL00_AHB0_FIFO_TYPE_REG __BIT(8) 88#define HW_DRAM_CTL00_RSVD1 __BITS(7, 1) 89#define HW_DRAM_CTL00_ADDR_CMP_EN __BIT(0) 90 91/* 92 * DRAM Control Register 1. 93 */ 94#define HW_DRAM_CTL01 0x004 95 96#define HW_DRAM_CTL01_RSVD4 __BITS(31, 25) 97#define HW_DRAM_CTL01_AHB2_FIFO_TYPE_REG __BIT(24) 98#define HW_DRAM_CTL01_RSVD3 __BITS(23, 17) 99#define HW_DRAM_CTL01_AHB1_W_PRIORITY __BIT(16) 100#define HW_DRAM_CTL01_RSVD2 __BITS(15, 9) 101#define HW_DRAM_CTL01_AHB1_R_PRIORITY __BIT(8) 102#define HW_DRAM_CTL01_RSVD1 __BITS(7, 1) 103#define HW_DRAM_CTL01_AHB1_FIFO_TYPE_REG __BIT(0) 104 105/* 106 * DRAM Control Register 2. 107 */ 108#define HW_DRAM_CTL02 0x008 109 110#define HW_DRAM_CTL02_RSVD4 __BITS(31, 25) 111#define HW_DRAM_CTL02_AHB3_R_PRIORITY __BIT(24) 112#define HW_DRAM_CTL02_RSVD3 __BITS(23, 17) 113#define HW_DRAM_CTL02_AHB3_FIFO_TYPE_REG __BIT(16) 114#define HW_DRAM_CTL02_RSVD2 __BIT(15, 9) 115#define HW_DRAM_CTL02_AHB2_W_PRIORITY __BIT(8) 116#define HW_DRAM_CTL02_RSVD1 __BITS(7, 1) 117#define HW_DRAM_CTL02_AHB2_R_PRIORITY __BIT(0) 118 119/* 120 * DRAM Control Register 3. 121 */ 122#define HW_DRAM_CTL03 0x00c 123 124#define HW_DRAM_CTL03_RSVD4 __BITS(31, 25) 125#define HW_DRAM_CTL03_AUTO_REFRESH_MODE __BIT(24) 126#define HW_DRAM_CTL03_RSVD3 __BITS(23, 17) 127#define HW_DRAM_CTL03_AREFRESH __BIT(16) 128#define HW_DRAM_CTL03_RSVD2 __BITS(15, 9) 129#define HW_DRAM_CTL03_AP __BIT(8) 130#define HW_DRAM_CTL03_RSVD1 __BITS(7, 1) 131#define HW_DRAM_CTL03_AHB3_W_PRIORITY __BIT(0) 132 133/* 134 * DRAM Control Register 4. 135 */ 136#define HW_DRAM_CTL04 0x010 137 138#define HW_DRAM_CTL04_RSVD4 __BITS(31, 25) 139#define HW_DRAM_CTL04_DLL_BYPASS_MODE __BIT(24) 140#define HW_DRAM_CTL04_RSVD3 __BITS(23, 17) 141#define HW_DRAM_CTL04_DLLLOCKREG __BIT(16) 142#define HW_DRAM_CTL04_RSVD2 __BITS(15, 9) 143#define HW_DRAM_CTL04_CONCURRENTAP __BIT(8) 144#define HW_DRAM_CTL04_RSVD1 __BITS(7, 1) 145#define HW_DRAM_CTL04_BANK_SPLIT_EN __BIT(0) 146 147/* 148 * DRAM Control Register 5. 149 */ 150#define HW_DRAM_CTL05 0x014 151 152#define HW_DRAM_CTL05_RSVD4 __BITS(31, 25) 153#define HW_DRAM_CTL05_INTRPTREADA __BIT(24) 154#define HW_DRAM_CTL05_RSVD3 __BITS(23, 17) 155#define HW_DRAM_CTL05_INTRPTAPBURST __BIT(16) 156#define HW_DRAM_CTL05_RSVD2 __BITS(15, 9) 157#define HW_DRAM_CTL05_FAST_WRITE __BIT(8) 158#define HW_DRAM_CTL05_RSVD1 __BITS(7, 1) 159#define HW_DRAM_CTL05_EN_LOWPOWER_MODE __BIT(0) 160 161/* 162 * DRAM Control Register 6. 163 */ 164#define HW_DRAM_CTL06 0x018 165 166#define HW_DRAM_CTL06_RSVD4 __BITS(31, 25) 167#define HW_DRAM_CTL06_POWER_DOWN __BIT(24) 168#define HW_DRAM_CTL06_RSVD3 __BITS(23, 17) 169#define HW_DRAM_CTL06_PLACEMENT_EN __BIT(16) 170#define HW_DRAM_CTL06_RSVD2 __BITS(15, 9) 171#define HW_DRAM_CTL06_NO_CMD_INIT __BIT(8) 172#define HW_DRAM_CTL06_RSVD1 __BITS(7, 1) 173#define HW_DRAM_CTL06_INTRPTWRITEA __BIT(0) 174 175/* 176 * DRAM Control Register 7. 177 */ 178#define HW_DRAM_CTL07 0x01c 179 180#define HW_DRAM_CTL07_RSVD4 __BITS(31, 25) 181#define HW_DRAM_CTL07_RW_SAME_EN __BIT(24) 182#define HW_DRAM_CTL07_RSVD3 __BITS(23, 17) 183#define HW_DRAM_CTL07_REG_DIMM_ENABLE __BIT(16) 184#define HW_DRAM_CTL07_RSVD2 __BITS(15, 9) 185#define HW_DRAM_CTL07_RD2RD_TURN __BIT(8) 186#define HW_DRAM_CTL07_RSVD1 __BITS(7, 1) 187#define HW_DRAM_CTL07_PRIORITY_EN __BIT(0) 188 189/* 190 * DRAM Control Register 8. 191 */ 192#define HW_DRAM_CTL08 0x020 193 194#define HW_DRAM_CTL08_RSVD4 __BITS(31, 25) 195#define HW_DRAM_CTL08_TRAS_LOCKOUT __BIT(24) 196#define HW_DRAM_CTL08_RSVD3 __BITS(23, 17) 197#define HW_DRAM_CTL08_START __BIT(16) 198#define HW_DRAM_CTL08_RSVD2 __BITS(15, 9) 199#define HW_DRAM_CTL08_SREFRESH __BIT(8) 200#define HW_DRAM_CTL08_RSVD1 __BITS(7, 1) 201#define HW_DRAM_CTL08_SDR_MODE __BIT(0) 202 203/* 204 * DRAM Control Register 9. 205 */ 206#define HW_DRAM_CTL09 0x024 207 208#define HW_DRAM_CTL09_RSVD4 __BITS(31, 26) 209#define HW_DRAM_CTL09_OUT_OF_RANGE_TYPE __BITS(25, 24) 210#define HW_DRAM_CTL09_RSVD3 __BITS(23, 18) 211#define HW_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID __BITS(17, 16) 212#define HW_DRAM_CTL09_RSVD2 __BITS(15, 9) 213#define HW_DRAM_CTL09_WRITE_MODEREG __BIT(8) 214#define HW_DRAM_CTL09_RSVD1 __BITS(7, 1) 215#define HW_DRAM_CTL09_WRITEINTERP __BIT(0) 216 217/* 218 * DRAM Control Register 10. 219 */ 220#define HW_DRAM_CTL10 0x028 221 222#define HW_DRAM_CTL10_RSVD4 __BITS(31, 27) 223#define HW_DRAM_CTL10_AGE_COUNT __BITS(26, 24) 224#define HW_DRAM_CTL10_RSVD3 __BITS(23, 19) 225#define HW_DRAM_CTL10_ADDR_PINS __BITS(18, 16) 226#define HW_DRAM_CTL10_RSVD2 __BITS(15, 10) 227#define HW_DRAM_CTL10_TEMRS __BITS(9, 8) 228#define HW_DRAM_CTL10_RSVD1 __BITS(7, 2) 229#define HW_DRAM_CTL10_Q_FULLNESS __BITS(1, 0) 230 231/* 232 * DRAM Control Register 11. 233 */ 234#define HW_DRAM_CTL11 0x02c 235 236#define HW_DRAM_CTL11_RSVD4 __BITS(31, 27) 237#define HW_DRAM_CTL11_MAX_CS_REG __BITS(26, 24) 238#define HW_DRAM_CTL11_RSVD3 __BITS(23, 19) 239#define HW_DRAM_CTL11_COMMAND_AGE_COUNT __BITS(18, 16) 240#define HW_DRAM_CTL11_RSVD2 __BITS(15, 11) 241#define HW_DRAM_CTL11_COLUMN_SIZE __BITS(10, 8) 242#define HW_DRAM_CTL11_RSVD1 __BITS(7, 3) 243#define HW_DRAM_CTL11_CASLAT __BITS(2, 0) 244 245/* 246 * DRAM Control Register 12. 247 */ 248#define HW_DRAM_CTL12 0x030 249 250#define HW_DRAM_CTL12_RSVD3 __BITS(31, 27) 251#define HW_DRAM_CTL12_TWR_INT __BITS(26, 24) 252#define HW_DRAM_CTL12_RSVD2 __BITS(23, 19) 253#define HW_DRAM_CTL12_TRRD __BITS(18 ,16) 254#define HW_DRAM_CTL12_OBSOLETE __BITS(15, 8) 255#define HW_DRAM_CTL12_RSVD1 __BITS(7, 3) 256#define HW_DRAM_CTL12_TCKE __BITS(2, 0) 257 258/* 259 * DRAM Control Register 13. 260 */ 261#define HW_DRAM_CTL13 0x034 262 263#define HW_DRAM_CTL13_RSVD4 __BITS(31, 28) 264#define HW_DRAM_CTL13_CASLAT_LIN_GATE __BITS(27, 24) 265#define HW_DRAM_CTL13_RSVD3 __BITS(23, 20) 266#define HW_DRAM_CTL13_CASLAT_LIN __BITS(19, 16) 267#define HW_DRAM_CTL13_RSVD2 __BITS(15, 12) 268#define HW_DRAM_CTL13_APREBIT __BITS(11, 8) 269#define HW_DRAM_CTL13_RSVD1 __BITS(7, 3) 270#define HW_DRAM_CTL13_TWTR __BITS(2, 0) 271 272/* 273 * DRAM Control Register 14. 274 */ 275#define HW_DRAM_CTL14 0x038 276 277#define HW_DRAM_CTL14_RSVD4 __BITS(31, 28) 278#define HW_DRAM_CTL14_MAX_COL_REG __BITS(27, 24) 279#define HW_DRAM_CTL14_RSVD3 __BITS(23, 20) 280#define HW_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE __BITS(19, 16) 281#define HW_DRAM_CTL14_RSVD2 __BITS(15, 12) 282#define HW_DRAM_CTL14_INITAREF __BITS(11, 8) 283#define HW_DRAM_CTL14_RSVD1 __BITS(7, 4) 284#define HW_DRAM_CTL14_CS_MAP __BITS(3, 0) 285 286/* 287 * DRAM Control Register 15. 288 */ 289#define HW_DRAM_CTL15 0x03c 290 291#define HW_DRAM_CTL15_RSVD4 __BITS(31, 28) 292#define HW_DRAM_CTL15_TRP __BITS(27, 24) 293#define HW_DRAM_CTL15_RSVD3 __BITS(23, 20) 294#define HW_DRAM_CTL15_TDAL __BITS(19, 16) 295#define HW_DRAM_CTL15_RSVD2 __BITS(15, 12) 296#define HW_DRAM_CTL15_PORT_BUSY __BITS(11, 8) 297#define HW_DRAM_CTL15_RSVD1 __BITS(7, 4) 298#define HW_DRAM_CTL15_MAX_ROW_REG __BITS(3, 0) 299 300/* 301 * DRAM Control Register 16. 302 */ 303#define HW_DRAM_CTL16 0x040 304 305#define HW_DRAM_CTL16_RSVD4 __BITS(31, 29) 306#define HW_DRAM_CTL16_TMRD __BITS(28, 24) 307#define HW_DRAM_CTL16_RSVD3 __BITS(23, 21) 308#define HW_DRAM_CTL16_LOWPOWER_CONTROL __BITS(20, 16) 309#define HW_DRAM_CTL16_RSVD2 __BITS(15, 13) 310#define HW_DRAM_CTL16_LOWPOWER_AUTO_ENABLE __BITS(12, 8) 311#define HW_DRAM_CTL16_RSVD1 __BITS(7, 4) 312#define HW_DRAM_CTL16_INT_ACK __BITS(3, 0) 313 314/* 315 * DRAM Control Register 17. 316 */ 317#define HW_DRAM_CTL17 0x044 318 319#define HW_DRAM_CTL17_DLL_START_POINT __BITS(31, 24) 320#define HW_DRAM_CTL17_DLL_LOCK __BITS(23, 16) 321#define HW_DRAM_CTL17_DLL_INCREMENT __BITS(15, 8) 322#define HW_DRAM_CTL17_RSVD1 __BITS(7, 5) 323#define HW_DRAM_CTL17_TRC __BITS(4, 0) 324 325/* 326 * DRAM Control Register 18. 327 */ 328#define HW_DRAM_CTL18 0x048 329 330#define HW_DRAM_CTL18_RSVD4 __BIT(31) 331#define HW_DRAM_CTL18_DLL_DQS_DELAY_1 __BITS(30, 24) 332#define HW_DRAM_CTL18_RSVD3 __BIT(23) 333#define HW_DRAM_CTL18_DLL_DQS_DELAY_0 __BITS(22, 16) 334#define HW_DRAM_CTL18_RSVD2 __BITS(15, 13) 335#define HW_DRAM_CTL18_INT_STATUS __BITS(12, 8) 336#define HW_DRAM_CTL18_RSVD1 __BITS(7, 5) 337#define HW_DRAM_CTL18_INT_MASK __BITS(4, 0) 338 339/* 340 * DRAM Control Register 19. 341 */ 342#define HW_DRAM_CTL19 0x04c 343 344#define HW_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS __BITS(31, 24) 345#define HW_DRAM_CTL19_RSVD1 __BIT(23) 346#define HW_DRAM_CTL19_DQS_OUT_SHIFT __BITS(22, 16) 347#define HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 __BITS(15, 8) 348#define HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 __BITS(7, 0) 349 350/* 351 * DRAM Control Register 20. 352 */ 353#define HW_DRAM_CTL20 0x050 354 355#define HW_DRAM_CTL20_TRCD_INT __BITS(31, 24) 356#define HW_DRAM_CTL20_TRAS_MIN __BITS(23, 16) 357#define HW_DRAM_CTL20_WR_DQS_SHIFT_BYPASS __BITS(15, 8) 358#define HW_DRAM_CTL20_RSVD1 __BIT(7) 359#define HW_DRAM_CTL20_WR_DQS_SHIFT __BITS(6, 0) 360 361/* 362 * DRAM Control Register 21. 363 */ 364#define HW_DRAM_CTL21 0x054 365 366#define HW_DRAM_CTL21_OBSOLETE __BITS(31, 24) 367#define HW_DRAM_CTL21_RSVD1 __BITS(23, 18) 368#define HW_DRAM_CTL21_OUT_OF_RANGE_LENGTH __BITS(17, 8) 369#define HW_DRAM_CTL21_TRFC __BITS(7, 0) 370 371/* 372 * DRAM Control Register 22. 373 */ 374#define HW_DRAM_CTL22 0x058 375 376#define HW_DRAM_CTL22_RSVD2 __BITS(31, 27) 377#define HW_DRAM_CTL22_AHB0_WRCNT __BITS(26, 16) 378#define HW_DRAM_CTL22_RSVD1 __BITS(15, 11) 379#define HW_DRAM_CTL22_AHB0_RDCNT __BITS(10, 0) 380 381/* 382 * DRAM Control Register 23. 383 */ 384#define HW_DRAM_CTL23 0x05c 385 386#define HW_DRAM_CTL23_RSVD2 __BITS(31, 27) 387#define HW_DRAM_CTL23_AHB1_WRCNT __BITS(26, 16) 388#define HW_DRAM_CTL23_RSVD1 __BITS(15, 11) 389#define HW_DRAM_CTL23_AHB1_RDCNT __BITS(10, 0) 390 391/* 392 * DRAM Control Register 24. 393 */ 394#define HW_DRAM_CTL24 0x060 395 396#define HW_DRAM_CTL24_RSVD2 __BITS(31, 27) 397#define HW_DRAM_CTL24_AHB2_WRCNT __BITS(26, 16) 398#define HW_DRAM_CTL24_RSVD1 __BITS(15, 11) 399#define HW_DRAM_CTL24_AHB2_RDCNT __BITS(10, 0) 400 401/* 402 * DRAM Control Register 25. 403 */ 404#define HW_DRAM_CTL25 0x064 405 406#define HW_DRAM_CTL25_RSVD2 __BITS(31, 27) 407#define HW_DRAM_CTL25_AHB3_WRCNT __BITS(26, 16) 408#define HW_DRAM_CTL25_RSVD1 __BITS(15, 11) 409#define HW_DRAM_CTL25_AHB3_RDCNT __BITS(10, 0) 410 411/* 412 * DRAM Control Register 26. 413 */ 414#define HW_DRAM_CTL26 0x068 415 416#define HW_DRAM_CTL26_OBSOLETE __BITS(31, 16) 417#define HW_DRAM_CTL26_RSVD1 __BITS(15, 12) 418#define HW_DRAM_CTL26_TREF __BITS(11, 0) 419 420/* 421 * DRAM Control Register 27. 422 */ 423#define HW_DRAM_CTL27 0x06c 424 425#define HW_DRAM_CTL27_OBSOLETE __BITS(31, 0) 426 427/* 428 * DRAM Control Register 28. 429 */ 430#define HW_DRAM_CTL28 0x070 431 432#define HW_DRAM_CTL28_OBSOLETE __BITS(31, 0) 433 434/* 435 * DRAM Control Register 29. 436 */ 437#define HW_DRAM_CTL29 0x074 438 439#define HW_DRAM_CTL29_LOWPOWER_INTERNAL_CNT __BITS(31, 16) 440#define HW_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT __BITS(15, 0) 441 442/* 443 * DRAM Control Register 30. 444 */ 445#define HW_DRAM_CTL30 0x078 446 447#define HW_DRAM_CTL30_LOWPOWER_REFRESH_HOLD __BITS(31, 16) 448#define HW_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT __BITS(15, 0) 449 450/* 451 * DRAM Control Register 31. 452 */ 453#define HW_DRAM_CTL31 0x07c 454 455#define HW_DRAM_CTL31_TDLL __BITS(31, 16) 456#define HW_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT __BITS(15, 0) 457 458/* 459 * DRAM Control Register 32. 460 */ 461#define HW_DRAM_CTL32 0x080 462 463#define HW_DRAM_CTL32_TXSNR __BITS(31, 16) 464#define HW_DRAM_CTL32_TRAS_MAX __BITS(15, 0) 465 466/* 467 * DRAM Control Register 33. 468 */ 469#define HW_DRAM_CTL33 0x084 470 471#define HW_DRAM_CTL33_VERSION __BITS(31, 16) 472#define HW_DRAM_CTL33_TXSR __BITS(15, 0) 473 474/* 475 * DRAM Control Register 34. 476 */ 477#define HW_DRAM_CTL34 0x088 478 479#define HW_DRAM_CTL34_RSVD1 __BITS(31, 24) 480#define HW_DRAM_CTL34_TINIT __BITS(23, 0) 481 482/* 483 * DRAM Control Register 35. 484 */ 485#define HW_DRAM_CTL35 0x08c 486 487#define HW_DRAM_CTL35_RSVD1 __BIT(31) 488#define HW_DRAM_CTL35_OUT_OF_RANGE_ADDR __BITS(30, 0) 489 490/* 491 * DRAM Control Register 36. 492 */ 493#define HW_DRAM_CTL36 0x090 494 495#define HW_DRAM_CTL36_RSVD5 __BITS(31, 25) 496#define HW_DRAM_CTL36_PWRUP_SREFRESH_EXIT __BIT(24) 497#define HW_DRAM_CTL36_RSVD4 __BITS(23, 17) 498#define HW_DRAM_CTL36_ENABLE_QUICK_SREFRESH __BIT(16) 499#define HW_DRAM_CTL36_RSVD3 __BITS(15, 9) 500#define HW_DRAM_CTL36_RSVD2 __BIT(8) 501#define HW_DRAM_CTL36_RSVD1 __BITS(7, 1) 502#define HW_DRAM_CTL36_ACTIVE_AGING __BIT(0) 503 504/* 505 * DRAM Control Register 37. 506 */ 507#define HW_DRAM_CTL37 0x094 508 509#define HW_DRAM_CTL37_OBSOLETE __BITS(31, 24) 510#define HW_DRAM_CTL37_RSVD2 __BITS(23, 18) 511#define HW_DRAM_CTL37_BUS_SHARE_TIMEOUT __BITS(17, 8) 512#define HW_DRAM_CTL37_RSVD1 __BITS(7, 1) 513#define HW_DRAM_CTL37_TREF_ENABLE __BIT(0) 514 515/* 516 * DRAM Control Register 38. 517 */ 518#define HW_DRAM_CTL38 0x098 519 520#define HW_DRAM_CTL38_RSVD2 __BITS(31, 29) 521#define HW_DRAM_CTL38_EMRS2_DATA_0 __BITS(28, 16) 522#define HW_DRAM_CTL38_RSVD1 __BITS(15, 13) 523#define HW_DRAM_CTL38_EMRS1_DATA __BITS(12, 0) 524 525/* 526 * DRAM Control Register 39. 527 */ 528#define HW_DRAM_CTL39 0x09c 529 530#define HW_DRAM_CTL39_RSVD2 __BITS(31, 29) 531#define HW_DRAM_CTL39_EMRS2_DATA_2 __BITS(28, 16) 532#define HW_DRAM_CTL39_RSVD1 __BITS(15, 13) 533#define HW_DRAM_CTL39_EMRS2_DATA_1 __BITS(12, 0) 534 535/* 536 * DRAM Control Register 40. 537 */ 538#define HW_DRAM_CTL40 0x0A0 539 540#define HW_DRAM_CTL40_TPDEX __BITS(31, 16) 541#define HW_DRAM_CTL40_RSVD1 __BITS(15, 13) 542#define HW_DRAM_CTL40_EMRS2_DATA_3 __BITS(12, 0) 543 544#endif /* !_ARM_IMX_IMX23_EMIREG_H_ */ 545