if_enetreg.h revision 1.2
1/* $NetBSD: if_enetreg.h,v 1.2 2016/05/17 06:44:45 ryo Exp $ */ 2 3/*- 4 * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * i.MX6,7 10/100/1000-Mbps ethernet MAC (ENET) 31 */ 32 33#ifndef _ARM_IMX_IF_ENETREG_H_ 34#define _ARM_IMX_IF_ENETREG_H_ 35 36#include <sys/cdefs.h> 37 38#define ENET_EIR 0x00000004 39# define ENET_EIR_BABR __BIT(30) 40# define ENET_EIR_BABT __BIT(29) 41# define ENET_EIR_GRA __BIT(28) 42# define ENET_EIR_TXF __BIT(27) 43# define ENET_EIR_TXB __BIT(26) 44# define ENET_EIR_RXF __BIT(25) 45# define ENET_EIR_RXB __BIT(24) 46# define ENET_EIR_MII __BIT(23) 47# define ENET_EIR_EBERR __BIT(22) 48# define ENET_EIR_LC __BIT(21) 49# define ENET_EIR_RL __BIT(20) 50# define ENET_EIR_UN __BIT(19) 51# define ENET_EIR_PLR __BIT(18) 52# define ENET_EIR_WAKEUP __BIT(17) 53# define ENET_EIR_TS_AVAIL __BIT(16) 54# define ENET_EIR_TS_TIMER __BIT(15) 55# define ENET_EIR_RXFLUSH_2 __BIT(14) /* imx7 */ 56# define ENET_EIR_RXFLUSH_1 __BIT(13) /* imx7 */ 57# define ENET_EIR_RXFLUSH_0 __BIT(12) /* imx7 */ 58# define ENET_EIR_TXF2 __BIT(7) /* imx7 */ 59# define ENET_EIR_TXB2 __BIT(6) /* imx7 */ 60# define ENET_EIR_RXF2 __BIT(5) /* imx7 */ 61# define ENET_EIR_RXB2 __BIT(4) /* imx7 */ 62# define ENET_EIR_TXF1 __BIT(3) /* imx7 */ 63# define ENET_EIR_TXB1 __BIT(2) /* imx7 */ 64# define ENET_EIR_RXF1 __BIT(1) /* imx7 */ 65# define ENET_EIR_RXB1 __BIT(1) /* imx7 */ 66#define ENET_EIMR 0x00000008 67#define ENET_RDAR 0x00000010 68# define ENET_RDAR_ACTIVE __BIT(24) 69#define ENET_TDAR 0x00000014 70# define ENET_TDAR_ACTIVE __BIT(24) 71 72#define ENET_ECR 0x00000024 73# define ENET_ECR_SVLANDBL __BIT(11) /* imx7 */ 74# define ENET_ECR_VLANUE2ND __BIT(10) /* imx7 */ 75# define ENET_ECR_SVLANEN __BIT(9) /* imx7 */ 76# define ENET_ECR_DBSWP __BIT(8) 77# define ENET_ECR_STOPEN __BIT(7) 78# define ENET_ECR_DBGEN __BIT(6) 79# define ENET_ECR_SPEED __BIT(5) 80# define ENET_ECR_EN1588 __BIT(4) 81# define ENET_ECR_SLEEP __BIT(3) 82# define ENET_ECR_MAGICEN __BIT(2) 83# define ENET_ECR_ETHEREN __BIT(1) 84# define ENET_ECR_RESET __BIT(0) 85#define ENET_MMFR 0x00000040 86# define ENET_MMFR_ST 0x40000000 87# define ENET_MMFR_OP_FORCEWRITE 0x00000000 88# define ENET_MMFR_OP_WRITE 0x10000000 89# define ENET_MMFR_OP_READ 0x20000000 90# define ENET_MMFR_OP_FORCEREAD 0x30000000 91# define ENET_MMFR_TA 0x00020000 92# define ENET_MMFR_PHY_ADDR(phy) __SHIFTIN(phy, __BITS(27, 23)) 93# define ENET_MMFR_PHY_REG(reg) __SHIFTIN(reg, __BITS(22, 18)) 94# define ENET_MMFR_DATAMASK 0x0000ffff 95#define ENET_MSCR 0x00000044 96# define ENET_MSCR_HOLDTIME_1CLK 0x00000000 97# define ENET_MSCR_HOLDTIME_2CLK 0x00000100 98# define ENET_MSCR_HOLDTIME_3CLK 0x00000200 99# define ENET_MSCR_HOLDTIME_8CLK 0x00000700 100# define ENET_MSCR_DIS_PRE __BIT(7) 101# define ENET_MSCR_MII_SPEED_25MHZ __SHIFTIN(4, __BITS(6, 1)) 102# define ENET_MSCR_MII_SPEED_33MHZ __SHIFTIN(6, __BITS(6, 1)) 103# define ENET_MSCR_MII_SPEED_40MHZ __SHIFTIN(7, __BITS(6, 1)) 104# define ENET_MSCR_MII_SPEED_50MHZ __SHIFTIN(9, __BITS(6, 1)) 105# define ENET_MSCR_MII_SPEED_66MHZ __SHIFTIN(13, __BITS(6, 1)) 106 107#define ENET_MIBC 0x00000064 108# define ENET_MIBC_MIB_DIS __BIT(31) 109# define ENET_MIBC_MIB_IDLE __BIT(30) 110# define ENET_MIBC_MIB_CLEAR __BIT(29) 111 112#define ENET_RCR 0x00000084 113# define ENET_RCR_GRS __BIT(31) 114# define ENET_RCR_NLC __BIT(30) 115# define ENET_RCR_MAX_FL(n) __SHIFTIN(n, __BITS(29, 16)) 116# define ENET_RCR_CFEN __BIT(15) 117# define ENET_RCR_CRCFWD __BIT(14) 118# define ENET_RCR_PAUFWD __BIT(13) 119# define ENET_RCR_PADEN __BIT(12) 120# define ENET_RCR_RMII_10T __BIT(9) 121# define ENET_RCR_RGMII_EN __BIT(6) 122# define ENET_RCR_FCE __BIT(5) 123# define ENET_RCR_PROM __BIT(3) 124# define ENET_RCR_DRT __BIT(1) 125 126#define ENET_TCR 0x000000c4 127# define ENET_TCR_FDEN __BIT(2) 128 129#define ENET_PALR 0x000000e4 130#define ENET_PAUR 0x000000e8 131#define ENET_OPD 0x000000ec 132 133#define ENET_TXIC0 0x000000f0 /* imx7 */ 134#define ENET_TXIC1 0x000000f4 /* imx7 */ 135#define ENET_TXIC2 0x000000f8 /* imx7 */ 136#define ENET_RXIC0 0x00000100 /* imx7 */ 137#define ENET_RXIC1 0x00000104 /* imx7 */ 138#define ENET_RXIC2 0x00000108 /* imx7 */ 139 140#define ENET_IAUR 0x00000118 141#define ENET_IALR 0x0000011c 142#define ENET_GAUR 0x00000120 143#define ENET_GALR 0x00000124 144#define ENET_TFWR 0x00000144 145# define ENET_TFWR_STRFWD __BIT(8) 146# define ENET_TFWR_FIFO(n) __SHIFTIN(((n) / 64), __BITS(5, 0)) 147 148#define ENET_RDSR1 0x00000160 /* imx7 */ 149#define ENET_TDSR1 0x00000164 /* imx7 */ 150#define ENET_MRBR1 0x00000168 /* imx7 */ 151#define ENET_RDSR2 0x0000016c /* imx7 */ 152#define ENET_TDSR2 0x00000170 /* imx7 */ 153#define ENET_MRBR2 0x00000174 /* imx7 */ 154 155#define ENET_RDSR 0x00000180 156#define ENET_TDSR 0x00000184 157#define ENET_MRBR 0x00000188 158#define ENET_RSFL 0x00000190 159#define ENET_RSEM 0x00000194 160#define ENET_RAEM 0x00000198 161#define ENET_RAFL 0x0000019c 162#define ENET_TSEM 0x000001a0 163#define ENET_TAEM 0x000001a4 164#define ENET_TAFL 0x000001a8 165#define ENET_TIPG 0x000001ac 166#define ENET_FTRL 0x000001b0 167#define ENET_TACC 0x000001c0 168# define ENET_TACC_PROCHK __BIT(4) 169# define ENET_TACC_IPCHK __BIT(3) 170# define ENET_TACC_SHIFT16 __BIT(0) 171#define ENET_RACC 0x000001c4 172# define ENET_RACC_SHIFT16 __BIT(7) 173# define ENET_RACC_LINEDIS __BIT(6) 174# define ENET_RACC_PRODIS __BIT(2) 175# define ENET_RACC_IPDIS __BIT(1) 176# define ENET_RACC_PADREM __BIT(0) 177 178#define ENET_RCMR1 0x000001c8 /* imx7 */ 179#define ENET_RCMR2 0x000001cc /* imx7 */ 180#define ENET_DMA1CFG 0x000001d8 /* imx7 */ 181#define ENET_DMA2CFG 0x000001dc /* imx7 */ 182#define ENET_RDAR1 0x000001e0 /* imx7 */ 183#define ENET_TDAR1 0x000001e4 /* imx7 */ 184#define ENET_RDAR2 0x000001e8 /* imx7 */ 185#define ENET_TDAR2 0x000001ec /* imx7 */ 186#define ENET_QOS 0x000001f0 /* imx7 */ 187 188/* Statistics counters */ 189#define ENET_RMON_T_DROP 0x00000200 190#define ENET_RMON_T_PACKETS 0x00000204 191#define ENET_RMON_T_BC_PKT 0x00000208 192#define ENET_RMON_T_MC_PKT 0x0000020c 193#define ENET_RMON_T_CRC_ALIGN 0x00000210 194#define ENET_RMON_T_UNDERSIZE 0x00000214 195#define ENET_RMON_T_OVERSIZE 0x00000218 196#define ENET_RMON_T_FRAG 0x0000021c 197#define ENET_RMON_T_JAB 0x00000220 198#define ENET_RMON_T_COL 0x00000224 199#define ENET_RMON_T_P64 0x00000228 200#define ENET_RMON_T_P65TO127N 0x0000022c 201#define ENET_RMON_T_P128TO255N 0x00000230 202#define ENET_RMON_T_P256TO511 0x00000234 203#define ENET_RMON_T_P512TO1023 0x00000238 204#define ENET_RMON_T_P1024TO2047 0x0000023c 205#define ENET_RMON_T_P_GTE2048 0x00000240 206#define ENET_RMON_T_OCTETS 0x00000244 207#define ENET_IEEE_T_DROP 0x00000248 208#define ENET_IEEE_T_FRAME_OK 0x0000024c 209#define ENET_IEEE_T_1COL 0x00000250 210#define ENET_IEEE_T_MCOL 0x00000254 211#define ENET_IEEE_T_DEF 0x00000258 212#define ENET_IEEE_T_LCOL 0x0000025c 213#define ENET_IEEE_T_EXCOL 0x00000260 214#define ENET_IEEE_T_MACERR 0x00000264 215#define ENET_IEEE_T_CSERR 0x00000268 216#define ENET_IEEE_T_SQE 0x0000026c 217#define ENET_IEEE_T_FDXFC 0x00000270 218#define ENET_IEEE_T_OCTETS_OK 0x00000274 219#define ENET_RMON_R_PACKETS 0x00000284 220#define ENET_RMON_R_BC_PKT 0x00000288 221#define ENET_RMON_R_MC_PKT 0x0000028c 222#define ENET_RMON_R_CRC_ALIGN 0x00000290 223#define ENET_RMON_R_UNDERSIZE 0x00000294 224#define ENET_RMON_R_OVERSIZE 0x00000298 225#define ENET_RMON_R_FRAG 0x0000029c 226#define ENET_RMON_R_JAB 0x000002a0 227#define ENET_RMON_R_RESVD_0 0x000002a4 228#define ENET_RMON_R_P64 0x000002a8 229#define ENET_RMON_R_P65TO127 0x000002ac 230#define ENET_RMON_R_P128TO255 0x000002b0 231#define ENET_RMON_R_P256TO511 0x000002b4 232#define ENET_RMON_R_P512TO1023 0x000002b8 233#define ENET_RMON_R_P1024TO2047 0x000002bc 234#define ENET_RMON_R_P_GTE2048 0x000002c0 235#define ENET_RMON_R_OCTETS 0x000002c4 236#define ENET_IEEE_R_DROP 0x000002c8 237#define ENET_IEEE_R_FRAME_OK 0x000002cc 238#define ENET_IEEE_R_CRC 0x000002d0 239#define ENET_IEEE_R_ALIGN 0x000002d4 240#define ENET_IEEE_R_MACERR 0x000002d8 241#define ENET_IEEE_R_FDXFC 0x000002dc 242#define ENET_IEEE_R_OCTETS_OK 0x000002e0 243 244/* IEEE1588 control */ 245#define ENET_ATCR 0x00000400 246#define ENET_ATVR 0x00000404 247#define ENET_ATOFF 0x00000408 248#define ENET_ATPER 0x0000040c 249#define ENET_ATCOR 0x00000410 250#define ENET_ATINC 0x00000414 251#define ENET_ATSTMP 0x00000418 252 253/* Capture/compare block */ 254#define ENET_TGSR 0x00000604 255#define ENET_TCSR0 0x00000608 256#define ENET_TCCR0 0x0000060c 257#define ENET_TCSR1 0x00000610 258#define ENET_TCCR1 0x00000614 259#define ENET_TCSR2 0x00000618 260#define ENET_TCCR2 0x0000061c 261#define ENET_TCSR3 0x00000620 262#define ENET_TCCR3 0x00000624 263 264#define AIPS_ENET_SIZE 0x00000800 265 266/* enhanced transmit buffer descriptor */ 267struct enet_txdesc { 268 uint32_t tx_flags1_len; 269#define TXFLAGS1_R __BIT(31) /* Ready */ 270#define TXFLAGS1_T1 __BIT(30) /* TX software owner1 */ 271#define TXFLAGS1_W __BIT(29) /* Wrap */ 272#define TXFLAGS1_T2 __BIT(28) /* TX software owner2 */ 273#define TXFLAGS1_L __BIT(27) /* Last in frame */ 274#define TXFLAGS1_TC __BIT(26) /* Transmit CRC */ 275#define TXFLAGS1_ABC __BIT(25) /* Append bad CRC */ 276#define TXFLAGS1_LEN(n) ((n) & 0xffff) 277 uint32_t tx_databuf; 278 uint32_t tx_flags2; 279#define TXFLAGS2_INT __BIT(30) /* Interrupt */ 280#define TXFLAGS2_TS __BIT(29) /* Timestamp */ 281#define TXFLAGS2_PINS __BIT(28) /* Insert Proto csum */ 282#define TXFLAGS2_IINS __BIT(27) /* Insert IP csum */ 283#define TXFLAGS2_TXE __BIT(15) /* Transmit error */ 284#define TXFLAGS2_UE __BIT(13) /* Underflow error */ 285#define TXFLAGS2_EE __BIT(12) /* Excess colls Err */ 286#define TXFLAGS2_FE __BIT(11) /* Frame Error */ 287#define TXFLAGS2_LCE __BIT(10) /* Late collision Err */ 288#define TXFLAGS2_OE __BIT(9) /* Overfow Error */ 289#define TXFLAGS2_TSE __BIT(8) /* Timestamp Error */ 290 uint32_t tx__reserved1; 291 uint32_t tx_flags3; 292#define TXFLAGS3_BDU __BIT(31) 293 uint32_t tx_1588timestamp; 294 uint32_t tx__reserved2; 295 uint32_t tx__reserved3; 296} __packed; 297 298/* enhanced receive buffer descriptor */ 299struct enet_rxdesc { 300 uint32_t rx_flags1_len; 301#define RXFLAGS1_E __BIT(31) /* Empty */ 302#define RXFLAGS1_R1 __BIT(30) /* RX software owner1 */ 303#define RXFLAGS1_W __BIT(29) /* Wrap */ 304#define RXFLAGS1_R2 __BIT(28) /* RX software owner2 */ 305#define RXFLAGS1_L __BIT(27) /* Last in frame */ 306#define RXFLAGS1_M __BIT(24) /* Miss */ 307#define RXFLAGS1_BC __BIT(23) /* Broadcast */ 308#define RXFLAGS1_MC __BIT(22) /* Multicast */ 309#define RXFLAGS1_LG __BIT(21) /* Length Violation */ 310#define RXFLAGS1_NO __BIT(20) /* Non-Octet aligned */ 311#define RXFLAGS1_CR __BIT(18) /* CRC or frame error */ 312#define RXFLAGS1_OV __BIT(17) /* Overrun */ 313#define RXFLAGS1_TR __BIT(16) /* Truncated */ 314#define RXFLAGS1_LEN(n) ((n) & 0xffff) 315 uint32_t rx_databuf; 316 uint32_t rx_flags2; 317#define RXFLAGS2_ME __BIT(31) /* MAC error */ 318#define RXFLAGS2_PE __BIT(26) /* PHY error */ 319#define RXFLAGS2_CE __BIT(25) /* Collision */ 320#define RXFLAGS2_UC __BIT(24) /* Unicast */ 321#define RXFLAGS2_INT __BIT(23) /* RXB/RXF interrupt */ 322#define RXFLAGS2_VPCP __BITS(15, 31) /* VLAN prio pts (imx7) */ 323#define RXFLAGS2_ICE __BIT(5) /* IP csum error */ 324#define RXFLAGS2_PCR __BIT(4) /* Proto csum error */ 325#define RXFLAGS2_VLAN __BIT(2) /* VLAN */ 326#define RXFLAGS2_IPV6 __BIT(1) /* IPv6 frame */ 327#define RXFLAGS2_FRAG __BIT(0) /* IPv4 fragment */ 328#if _BYTE_ORDER == _LITTLE_ENDIAN 329 uint16_t rx_cksum; 330 uint8_t rx_proto; 331 uint8_t rx_hl; 332#else 333 uint8_t rx_hl; 334 uint8_t rx_proto; 335 uint16_t rx_cksum; 336#endif 337 uint32_t rx_flags3; 338#define RXFLAGS3_BDU __BIT(31) 339 uint32_t rx_1588timestamp; 340 uint32_t rx__reserved2; 341 uint32_t rx__reserved3; 342} __packed; 343 344#endif /* _ARM_IMX_IF_ENETREG_H_ */ 345