11844Swollman/* $NetBSD: pcihost_fdtvar.h,v 1.5 2022/09/06 11:55:07 skrll Exp $ */ 250476Speter 31844Swollman/*- 41638Srgrimes * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca> 594940Sru * All rights reserved. 61638Srgrimes * 71844Swollman * Redistribution and use in source and binary forms, with or without 81844Swollman * modification, are permitted provided that the following conditions 938655Sjb * are met: 101844Swollman * 1. Redistributions of source code must retain the above copyright 111844Swollman * notice, this list of conditions and the following disclaimer. 1228945Speter * 2. Redistributions in binary form must reproduce the above copyright 131844Swollman * notice, this list of conditions and the following disclaimer in the 1442915Sjdp * documentation and/or other materials provided with the distribution. 1542915Sjdp * 1642915Sjdp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1742915Sjdp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1842915Sjdp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1942915Sjdp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2042915Sjdp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2142915Sjdp * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2242915Sjdp * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2342915Sjdp * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2442915Sjdp * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2542915Sjdp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2629141Speter * SUCH DAMAGE. 2742915Sjdp */ 2842915Sjdp 2942915Sjdp/* Physical address format bit definitions */ 3042915Sjdp#define PHYS_HI_RELO __BIT(31) 3142915Sjdp#define PHYS_HI_PREFETCH __BIT(30) 3242915Sjdp#define PHYS_HI_ALIASED __BIT(29) 3342915Sjdp#define PHYS_HI_SPACE __BITS(25,24) 3429141Speter#define PHYS_HI_SPACE_CFG 0 352827Sjkh#define PHYS_HI_SPACE_IO 1 362827Sjkh#define PHYS_HI_SPACE_MEM32 2 372827Sjkh#define PHYS_HI_SPACE_MEM64 3 382827Sjkh#define PHYS_HI_BUS __BITS(23,16) 392827Sjkh#define PHYS_HI_DEVICE __BITS(15,11) 401638Srgrimes#define PHYS_HI_FUNCTION __BITS(10,8) 412827Sjkh#define PHYS_HI_REGISTER __BITS(7,0) 421638Srgrimes 4343055Sjdpextern int pcihost_segment; 4418529Sbde 4531809Sbdeenum pcihost_type { 4618529Sbde PCIHOST_CAM = 1, 471638Srgrimes PCIHOST_ECAM, 4842450Sjdp}; 491638Srgrimes 5095064Sobrienstruct pcihost_msi_handlers; 511638Srgrimes 5292491Smarkmstruct pcih_bus_space { 5392491Smarkm struct bus_space bst; 5492553Sru 5592491Smarkm int (*map)(void *, bus_addr_t, bus_size_t, 5692491Smarkm int, bus_space_handle_t *); 5792553Sru int flags; 5892553Sru 5992491Smarkm struct space_range { 601638Srgrimes bus_addr_t bpci; 611844Swollman bus_addr_t bbus; 6238186Speter bus_size_t size; 6338186Speter } ranges[4]; 641638Srgrimes size_t nranges; 651638Srgrimes}; 6624761Sjdp 6738186Speterstruct pcihost_softc { 6838186Speter device_t sc_dev; 691638Srgrimes bus_dma_tag_t sc_dmat; 7042450Sjdp bus_space_tag_t sc_bst; 711844Swollman bus_space_handle_t sc_bsh; 7238186Speter bus_space_tag_t sc_pci_bst; 7338186Speter int sc_phandle; 741844Swollman 7536673Sdt enum pcihost_type sc_type; 761844Swollman 7738186Speter u_int sc_seg; 7838186Speter u_int sc_bus_min; 791844Swollman u_int sc_bus_max; 8036673Sdt 8124761Sjdp struct arm32_pci_chipset sc_pc; 8238186Speter 8338186Speter struct pcih_bus_space sc_io; 841844Swollman struct pcih_bus_space sc_mem; 8542450Sjdp 861844Swollman int sc_pci_flags; 8738186Speter 8838186Speter const u_int *sc_pci_ranges; 891844Swollman u_int sc_pci_ranges_cells; 901844Swollman 911844Swollman kmutex_t sc_msi_handlers_mutex; 9238186Speter LIST_HEAD(, pcihost_msi_handler) 9338186Speter sc_msi_handlers; 941844Swollman}; 951844Swollman 9624761Sjdpvoid pcihost_init2(struct pcihost_softc *); 9738186Spetervoid pcihost_init(pci_chipset_tag_t, void *); 9838186Speter