pcihost_fdt.c revision 1.17
1/* $NetBSD: pcihost_fdt.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $"); 31 32#include <sys/param.h> 33 34#include <sys/bus.h> 35#include <sys/device.h> 36#include <sys/intr.h> 37#include <sys/kernel.h> 38#include <sys/kmem.h> 39#include <sys/lwp.h> 40#include <sys/mutex.h> 41#include <sys/queue.h> 42#include <sys/systm.h> 43 44#include <machine/cpu.h> 45 46#include <arm/cpufunc.h> 47 48#include <dev/pci/pcireg.h> 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pciconf.h> 51 52#include <dev/fdt/fdtvar.h> 53 54#include <arm/pci/pci_msi_machdep.h> 55#include <arm/fdt/pcihost_fdtvar.h> 56 57#define PCIHOST_DEFAULT_BUS_MIN 0 58#define PCIHOST_DEFAULT_BUS_MAX 255 59 60#define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62int pcihost_segment = 0; 63 64static int pcihost_match(device_t, cfdata_t, void *); 65static void pcihost_attach(device_t, device_t, void *); 66 67static int pcihost_config(struct pcihost_softc *); 68 69static void pcihost_attach_hook(device_t, device_t, 70 struct pcibus_attach_args *); 71static int pcihost_bus_maxdevs(void *, int); 72static pcitag_t pcihost_make_tag(void *, int, int, int); 73static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 74static u_int pcihost_get_segment(void *); 75static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 76static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 77static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 78static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 79 80static int pcihost_intr_map(const struct pci_attach_args *, 81 pci_intr_handle_t *); 82static const char *pcihost_intr_string(void *, pci_intr_handle_t, 83 char *, size_t); 84static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 85static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 86 uint64_t); 87static void * pcihost_intr_establish(void *, pci_intr_handle_t, 88 int, int (*)(void *), void *, 89 const char *); 90static void pcihost_intr_disestablish(void *, void *); 91 92static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 93 int, bus_space_handle_t *); 94 95CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 96 pcihost_match, pcihost_attach, NULL, NULL); 97 98static const struct of_compat_data compat_data[] = { 99 { "pci-host-cam-generic", PCIHOST_CAM }, 100 { "pci-host-ecam-generic", PCIHOST_ECAM }, 101 { NULL, 0 } 102}; 103 104static int 105pcihost_match(device_t parent, cfdata_t cf, void *aux) 106{ 107 struct fdt_attach_args * const faa = aux; 108 109 return of_match_compat_data(faa->faa_phandle, compat_data); 110} 111 112static void 113pcihost_attach(device_t parent, device_t self, void *aux) 114{ 115 struct pcihost_softc * const sc = device_private(self); 116 struct fdt_attach_args * const faa = aux; 117 bus_addr_t cs_addr; 118 bus_size_t cs_size; 119 int error; 120 121 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 122 aprint_error(": couldn't get registers\n"); 123 return; 124 } 125 126 sc->sc_dev = self; 127 sc->sc_dmat = faa->faa_dmat; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_phandle = faa->faa_phandle; 130 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 131 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh); 132 if (error) { 133 aprint_error(": couldn't map registers: %d\n", error); 134 return; 135 } 136 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 137 138#ifdef __HAVE_PCI_MSI_MSIX 139 if (sc->sc_type == PCIHOST_ECAM) { 140 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 141 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 142 } 143#endif 144 145 aprint_naive("\n"); 146 aprint_normal(": Generic PCI host controller\n"); 147 148 pcihost_init(&sc->sc_pc, sc); 149 pcihost_init2(sc); 150} 151 152void 153pcihost_init2(struct pcihost_softc *sc) 154{ 155 struct pcibus_attach_args pba; 156 const u_int *data; 157 int len; 158 159 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 160 if (len != 8) { 161 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 162 return; 163 } 164 sc->sc_bus_min = be32toh(data[0]); 165 sc->sc_bus_max = be32toh(data[1]); 166 } else { 167 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 168 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 169 } 170 171 /* 172 * Assign a fixed PCI segment ("domain") number. If the property is not 173 * present, assign one. The binding spec says if this property is used to 174 * assign static segment numbers, all host bridges should have segments 175 * astatic assigned to prevent overlaps. 176 */ 177 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 178 sc->sc_seg = pcihost_segment++; 179 180 if (pcihost_config(sc) != 0) 181 return; 182 183 memset(&pba, 0, sizeof(pba)); 184 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 185 PCI_FLAGS_MRM_OKAY | 186 PCI_FLAGS_MWI_OKAY | 187 sc->sc_pci_flags; 188 pba.pba_iot = &sc->sc_io.bst; 189 pba.pba_memt = &sc->sc_mem.bst; 190 pba.pba_dmat = sc->sc_dmat; 191#ifdef _PCI_HAVE_DMA64 192 pba.pba_dmat64 = sc->sc_dmat; 193#endif 194 pba.pba_pc = &sc->sc_pc; 195 pba.pba_bus = sc->sc_bus_min; 196 197 config_found_ia(sc->sc_dev, "pcibus", &pba, pcibusprint); 198} 199 200void 201pcihost_init(pci_chipset_tag_t pc, void *priv) 202{ 203 pc->pc_conf_v = priv; 204 pc->pc_attach_hook = pcihost_attach_hook; 205 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 206 pc->pc_make_tag = pcihost_make_tag; 207 pc->pc_decompose_tag = pcihost_decompose_tag; 208 pc->pc_get_segment = pcihost_get_segment; 209 pc->pc_conf_read = pcihost_conf_read; 210 pc->pc_conf_write = pcihost_conf_write; 211 pc->pc_conf_hook = pcihost_conf_hook; 212 pc->pc_conf_interrupt = pcihost_conf_interrupt; 213 214 pc->pc_intr_v = priv; 215 pc->pc_intr_map = pcihost_intr_map; 216 pc->pc_intr_string = pcihost_intr_string; 217 pc->pc_intr_evcnt = pcihost_intr_evcnt; 218 pc->pc_intr_setattr = pcihost_intr_setattr; 219 pc->pc_intr_establish = pcihost_intr_establish; 220 pc->pc_intr_disestablish = pcihost_intr_disestablish; 221} 222 223static int 224pcihost_config(struct pcihost_softc *sc) 225{ 226 const u_int *ranges; 227 u_int probe_only; 228 int error, len, type; 229 bool swap; 230 231 struct pcih_bus_space * const pibs = &sc->sc_io; 232 pibs->bst = *sc->sc_bst; 233 pibs->bst.bs_cookie = pibs; 234 pibs->map = pibs->bst.bs_map; 235 pibs->flags = PCI_FLAGS_IO_OKAY; 236 pibs->bst.bs_map = pcihost_bus_space_map; 237 238 struct pcih_bus_space * const pmbs = &sc->sc_mem; 239 pmbs->bst = *sc->sc_bst; 240 pmbs->bst.bs_cookie = pmbs; 241 pmbs->map = pmbs->bst.bs_map; 242 pmbs->flags = PCI_FLAGS_MEM_OKAY; 243 pmbs->bst.bs_map = pcihost_bus_space_map; 244 245 /* 246 * If this flag is set, skip configuration of the PCI bus and use existing config. 247 */ 248 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 249 probe_only = 0; 250 if (probe_only) 251 return 0; 252 253 if (sc->sc_pci_ranges != NULL) { 254 ranges = sc->sc_pci_ranges; 255 len = sc->sc_pci_ranges_cells * 4; 256 swap = false; 257 } else { 258 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 259 if (ranges == NULL) { 260 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 261 return EINVAL; 262 } 263 swap = true; 264 } 265 266 struct pciconf_resources *pcires = pciconf_resource_init(); 267 268 /* 269 * Each entry in the ranges table contains: 270 * - bus address (3 cells) 271 * - cpu physical address (2 cells) 272 * - size (2 cells) 273 * Total size for each entry is 28 bytes (7 cells). 274 */ 275 while (len >= 28) { 276#define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 277#define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 278 const uint32_t phys_hi = DECODE32(ranges, 0); 279 uint64_t bus_phys = DECODE64(ranges, 1); 280 const uint64_t cpu_phys = DECODE64(ranges, 3); 281 uint64_t size = DECODE64(ranges, 5); 282#undef DECODE32 283#undef DECODE64 284 285 len -= 28; 286 ranges += 7; 287 288 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 289 PHYS_HI_SPACE_MEM64) ? true : false; 290 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 291 case PHYS_HI_SPACE_IO: 292 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 293 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 294 continue; 295 } 296 pibs->ranges[pibs->nranges].bpci = bus_phys; 297 pibs->ranges[pibs->nranges].bbus = cpu_phys; 298 pibs->ranges[pibs->nranges].size = size; 299 ++pibs->nranges; 300 aprint_verbose_dev(sc->sc_dev, 301 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 302 bus_phys, size, cpu_phys); 303 /* 304 * Reserve a PC-like legacy IO ports range, perhaps 305 * for access to VGA registers. 306 */ 307 if (bus_phys == 0 && size >= 0x10000) { 308 bus_phys += 0x1000; 309 size -= 0x1000; 310 } 311 error = pciconf_resource_add(pcires, 312 PCICONF_RESOURCE_IO, bus_phys, size); 313 if (error == 0) 314 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 315 break; 316 case PHYS_HI_SPACE_MEM64: 317 /* FALLTHROUGH */ 318 case PHYS_HI_SPACE_MEM32: 319 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 320 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 321 continue; 322 } 323 /* both pmem and mem spaces are in the same tag */ 324 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 325 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 326 pmbs->ranges[pmbs->nranges].size = size; 327 ++pmbs->nranges; 328 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 329 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 330 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 331 aprint_verbose_dev(sc->sc_dev, 332 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 333 is64 ? 64 : 32, bus_phys, size, cpu_phys); 334 } else { 335 type = PCICONF_RESOURCE_MEM; 336 aprint_verbose_dev(sc->sc_dev, 337 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 338 is64 ? 64 : 32, bus_phys, size, cpu_phys); 339 } 340 error = pciconf_resource_add(pcires, type, bus_phys, 341 size); 342 if (error == 0) 343 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 344 break; 345 default: 346 break; 347 } 348 } 349 350 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 351 PCIHOST_CACHELINE_SIZE); 352 353 pciconf_resource_fini(pcires); 354 355 if (error) { 356 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 357 return error; 358 } 359 360 return 0; 361} 362 363static void 364pcihost_attach_hook(device_t parent, device_t self, 365 struct pcibus_attach_args *pba) 366{ 367} 368 369static int 370pcihost_bus_maxdevs(void *v, int busno) 371{ 372 return 32; 373} 374 375static pcitag_t 376pcihost_make_tag(void *v, int b, int d, int f) 377{ 378 return (b << 16) | (d << 11) | (f << 8); 379} 380 381static void 382pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 383{ 384 if (bp) 385 *bp = (tag >> 16) & 0xff; 386 if (dp) 387 *dp = (tag >> 11) & 0x1f; 388 if (fp) 389 *fp = (tag >> 8) & 0x7; 390} 391 392static u_int 393pcihost_get_segment(void *v) 394{ 395 struct pcihost_softc *sc = v; 396 397 return sc->sc_seg; 398} 399 400static pcireg_t 401pcihost_conf_read(void *v, pcitag_t tag, int offset) 402{ 403 struct pcihost_softc *sc = v; 404 int b, d, f; 405 u_int reg; 406 407 pcihost_decompose_tag(v, tag, &b, &d, &f); 408 409 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 410 return (pcireg_t) -1; 411 412 if (sc->sc_type == PCIHOST_CAM) { 413 if (offset & ~0xff) 414 return (pcireg_t) -1; 415 reg = (b << 16) | (d << 11) | (f << 8) | offset; 416 } else if (sc->sc_type == PCIHOST_ECAM) { 417 if (offset & ~0xfff) 418 return (pcireg_t) -1; 419 reg = (b << 20) | (d << 15) | (f << 12) | offset; 420 } else { 421 return (pcireg_t) -1; 422 } 423 424 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 425} 426 427static void 428pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 429{ 430 struct pcihost_softc *sc = v; 431 int b, d, f; 432 u_int reg; 433 434 pcihost_decompose_tag(v, tag, &b, &d, &f); 435 436 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 437 return; 438 439 if (sc->sc_type == PCIHOST_CAM) { 440 if (offset & ~0xff) 441 return; 442 reg = (b << 16) | (d << 11) | (f << 8) | offset; 443 } else if (sc->sc_type == PCIHOST_ECAM) { 444 if (offset & ~0xfff) 445 return; 446 reg = (b << 20) | (d << 15) | (f << 12) | offset; 447 } else { 448 return; 449 } 450 451 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 452} 453 454static int 455pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 456{ 457 return PCI_CONF_DEFAULT; 458} 459 460static void 461pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 462{ 463} 464 465static int 466pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 467{ 468 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 469 u_int addr_cells, interrupt_cells; 470 const u_int *imap, *imask; 471 int imaplen, imasklen; 472 u_int match[4]; 473 int index; 474 475 if (pa->pa_intrpin == 0) 476 return EINVAL; 477 478 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 479 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 480 if (imap == NULL || imask == NULL || imasklen != 16) 481 return EINVAL; 482 483 /* Convert attach args to specifier */ 484 match[0] = htobe32( 485 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 486 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 487 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 488 ) & imask[0]; 489 match[1] = htobe32(0) & imask[1]; 490 match[2] = htobe32(0) & imask[2]; 491 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 492 493 index = 0; 494 while (imaplen >= 20) { 495 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 496 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 497 addr_cells = 2; 498 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 499 interrupt_cells = 0; 500 if (imaplen < (addr_cells + interrupt_cells) * 4) 501 return ENXIO; 502 503 if ((imap[0] & imask[0]) == match[0] && 504 (imap[1] & imask[1]) == match[1] && 505 (imap[2] & imask[2]) == match[2] && 506 (imap[3] & imask[3]) == match[3]) { 507 *ih = index; 508 return 0; 509 } 510 511 imap += (5 + addr_cells + interrupt_cells); 512 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 513 index++; 514 } 515 516 return EINVAL; 517} 518 519static const u_int * 520pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 521{ 522 u_int addr_cells, interrupt_cells; 523 int imaplen, index; 524 const u_int *imap; 525 526 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 527 KASSERT(imap != NULL); 528 529 index = 0; 530 while (imaplen >= 20) { 531 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 532 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 533 addr_cells = 2; 534 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 535 interrupt_cells = 0; 536 if (imaplen < (addr_cells + interrupt_cells) * 4) 537 return NULL; 538 539 if (index == ih) { 540 *pihandle = map_ihandle; 541 return imap + 5 + addr_cells; 542 } 543 544 imap += (5 + addr_cells + interrupt_cells); 545 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 546 index++; 547 } 548 549 return NULL; 550} 551 552static const char * 553pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 554{ 555 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 556 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 557 struct pcihost_softc *sc = v; 558 const u_int *specifier; 559 int ihandle; 560 561 if (ih & ARM_PCI_INTR_MSIX) { 562 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 563 } else if (ih & ARM_PCI_INTR_MSI) { 564 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 565 } else { 566 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 567 if (specifier == NULL) 568 return NULL; 569 570 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 571 return NULL; 572 } 573 574 return buf; 575} 576 577const struct evcnt * 578pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 579{ 580 return NULL; 581} 582 583static int 584pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 585{ 586 switch (attr) { 587 case PCI_INTR_MPSAFE: 588 if (data) 589 *ih |= ARM_PCI_INTR_MPSAFE; 590 else 591 *ih &= ~ARM_PCI_INTR_MPSAFE; 592 return 0; 593 default: 594 return ENODEV; 595 } 596} 597 598static void * 599pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 600 int (*callback)(void *), void *arg, const char *xname) 601{ 602 struct pcihost_softc *sc = v; 603 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 604 const u_int *specifier; 605 int ihandle; 606 607 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 608 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 609 610 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 611 if (specifier == NULL) 612 return NULL; 613 614 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 615} 616 617static void 618pcihost_intr_disestablish(void *v, void *vih) 619{ 620 struct pcihost_softc *sc = v; 621 622 fdtbus_intr_disestablish(sc->sc_phandle, vih); 623} 624 625static int 626pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 627 bus_space_handle_t *bshp) 628{ 629 struct pcih_bus_space * const pbs = t; 630 631 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 632 /* Force strongly ordered mapping for all I/O space */ 633 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 634 } 635 636 for (size_t i = 0; i < pbs->nranges; i++) { 637 const bus_addr_t rmin = pbs->ranges[i].bpci; 638 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 639 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 640 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 641 } 642 } 643 644 return ERANGE; 645} 646