1183371Simp/* $NetBSD: a9tmr_reg.h,v 1.3 2021/10/02 20:52:09 skrll Exp $ */ 2183371Simp/*- 3183371Simp * Copyright (c) 2012 The NetBSD Foundation, Inc. 4183371Simp * All rights reserved. 5183371Simp * 6183371Simp * This code is derived from software contributed to The NetBSD Foundation 7183371Simp * by Matt Thomas of 3am Software Foundry. 8183371Simp * 9183371Simp * Redistribution and use in source and binary forms, with or without 10183371Simp * modification, are permitted provided that the following conditions 11183371Simp * are met: 12183371Simp * 1. Redistributions of source code must retain the above copyright 13183371Simp * notice, this list of conditions and the following disclaimer. 14183371Simp * 2. Redistributions in binary form must reproduce the above copyright 15183371Simp * notice, this list of conditions and the following disclaimer in the 16183371Simp * documentation and/or other materials provided with the distribution. 17183371Simp * 18183371Simp * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19183371Simp * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20183371Simp * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21183371Simp * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22183371Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23183371Simp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24183371Simp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25183371Simp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26183371Simp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27183371Simp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28183371Simp * POSSIBILITY OF SUCH DAMAGE. 29183371Simp */ 30183371Simp 31183371Simp/* 32183371Simp * ARM MPCORE Global Timer Register Definitions 33183371Simp * 34183371Simp * These registers are accessible through a dedicated internal bus. 35203944Sweongyo * All accesses must be done in a little-endian manner. 36183371Simp * The base address of the pages containing these registers is defined 37203319Sweongyo * by the pins PERIPHBASE[31:13] which can be obtained by doing a 38203319Sweongyo * MRC p15,4,<Rd>,c15,c0,0; Read Configuration Base Address Register 39203319Sweongyo * (except cortex-A9 uniprocessor) 40203319Sweongyo * 41203319Sweongyo */ 42203319Sweongyo 43203319Sweongyo#ifndef _ARM_CORTEX_A9TMR_REG_H_ 44203319Sweongyo#define _ARM_CORTEX_A9TMR_REG_H_ 45203319Sweongyo 46203319Sweongyo#define TMR_GLOBAL_BASE 0x0200 // Offset in PeriphBase 47203319Sweongyo#define TMR_PRIVATE_BASE 0x0600 48203319Sweongyo#define TMR_WDOG_BASE 0x0620 49203319Sweongyo#define TMR_GLOBAL_SIZE 0x0100 50203319Sweongyo#define TMR_PRIVATE_SIZE 0x0020 51203319Sweongyo#define TMR_WDOG_SIZE 0x0020 52203319Sweongyo 53203319Sweongyo/* 54203319Sweongyo * F(timer) = PeriphClk / ((PreScaler_Value + 1) * Load_Value + 1)) 55203319Sweongyo */ 56203319Sweongyo#define TMR_LOAD 0x0000 // Timer Load Register 57203319Sweongyo#define TMR_CTR 0x0004 // Timer Counter Register 58203319Sweongyo#define TMR_CTL 0x0008 // Timer Control Register 59203319Sweongyo#define TMR_INT 0x000C // Timer Interrupt Status 60203319Sweongyo#define TMR_WDOGRST 0x0010 // Timer Reset Status (WDOG only) 61203319Sweongyo#define TMR_WDOGDIS 0x0014 // [WO] Timer Disable (WDOG only) 62203319Sweongyo 63203319Sweongyo#define TMR_CTL_PRESCALER __BITS(15,8) 64203319Sweongyo#define TMR_CTL_WDOG_MODE __BIT(3) // WDOG mode 65203319Sweongyo#define TMR_CTL_INT_ENABLE __BIT(2) // INT 29/30 is enabled 66203319Sweongyo#define TMR_CTL_AUTO_RELOAD __BIT(1) 67203319Sweongyo#define TMR_CTL_ENABLE __BIT(0) 68203319Sweongyo 69203319Sweongyo#define TMR_INT_EVENT __BIT(0) // [W1C] timer reached 0 70203319Sweongyo#define TMR_RST_EVENT __BIT(0) // [W1C] wdog timer reached 0 71203319Sweongyo 72203319Sweongyo#define TMR_WDOG_DISABLE_MAGIC1 0x12345678 73203319Sweongyo#define TMR_WDOG_DISABLE_MAGIC2 0x87654321 74203319Sweongyo 75203319Sweongyo/* 76203319Sweongyo * Global Timer is a 64-bit incrementing counter. As much as we'd like to 77203319Sweongyo * be able to use LDRD for loading the 64-bit counter, we aren't allowed to. 78203319Sweongyo */ 79203319Sweongyo#define TMR_GBL_CTR_L 0x000 // Global Timer 64-bit Lower Value 80203319Sweongyo#define TMR_GBL_CTR_U 0x004 // Global Timer 64-bit Upper Timer 81203319Sweongyo#define TMR_GBL_CTL 0x008 // Global Timer Control 82203319Sweongyo#define TMR_GBL_INT 0x00c // [L] Global Timer Interrupt Status 83203319Sweongyo#define TMR_GBL_CMP_L 0x010 // [L] Global Timer 64-bit Comparator Low 84203319Sweongyo#define TMR_GBL_CMP_H 0x014 // [L] Global Timer 64-bit Comparator High 85203319Sweongyo#define TMR_GBL_AUTOINC 0x018 // [L] Global Timer Auto-Increment 86203319Sweongyo 87203319Sweongyo#define TMR_GBL_CTL_PRESCALER __BIT(15,8) 88203319Sweongyo#define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled 89203319Sweongyo#define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled 90203319Sweongyo#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked] 91203319Sweongyo#define TMR_GBL_CTL_ENABLE __BIT(0) 92203319Sweongyo 93203319Sweongyo#endif /* !_ARM_CORTEX_A9TMR_REG_H_ */ 94203319Sweongyo