1/* $Id: at91tcreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 2/* $NetBSD: at91tcreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 3 4/*- 5 * Copyright (c) 2007 Embedtronics Oy 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#ifndef _AT91TCREG_H_ 31#define _AT91TCREG_H_ 1 32 33/* Timer Counter (TC), 34 * at91rm9200.pdf, Page 485 */ 35 36/* channel registers: */ 37#define TCC_COUNT 3 38 39#define TC_CCR 0x00U /* 0x00: Channel Control Register */ 40#define TC_CMR 0x04U /* 0x04: Channel Mode Register */ 41#define TC_CV 0x10U /* 0x10: Counter Value */ 42#define TC_RA 0x14U /* 0x14: Register A */ 43#define TC_RB 0x18U /* 0x18: Register B */ 44#define TC_RC 0x1CU /* 0x1C: Register C */ 45#define TC_SR 0x20U /* 0x20: Status Register */ 46#define TC_IER 0x24U /* 0x24: Interrupt Enable Register */ 47#define TC_IDR 0x28U /* 0x28: Interrupt Disable Register */ 48#define TC_IMR 0x2CU /* 0x2C: Interrupt Mask Register */ 49 50/* Channel Control Register bits: */ 51#define TC_CCR_SWTRG 0x00000004U /* 1 = software trigger command */ 52#define TC_CCR_CLKDIS 0x00000002U /* 1 = disable clock */ 53#define TC_CCR_CLKEN 0x00000001U /* 1 = enable clock */ 54 55 56/* Channel Mode Register bits in both modes : */ 57#define TC_CMR_WAVE 0x00008000U /* 1 = waveform mode (not capture) */ 58 59#define TC_CMR_BURST 0x00000030U /* burst signal selection */ 60#define TC_CMR_BURST_SHIFT 4U 61#define TC_CMR_BURST_NONE 0x00000000U 62#define TC_CMR_BURST_XC0 0x00000010U 63#define TC_CMR_BURST_XC1 0x00000020U 64#define TC_CMR_BURST_XC2 0x00000030U 65 66#define TC_CMR_CLKI 0x00000008U /* 1 = increment on falling edge */ 67 68#define TC_CMR_TCCLKS 0x00000007U /* clock selection */ 69#define TC_CMR_TCCLKS_SHIFT 0U 70#define TC_CMR_TCCLKS_CLOCK1 0x00000000U 71#define TC_CMR_TCCLKS_CLOCK2 0x00000001U 72#define TC_CMR_TCCLKS_CLOCK3 0x00000002U 73#define TC_CMR_TCCLKS_CLOCK4 0x00000003U 74#define TC_CMR_TCCLKS_CLOCK5 0x00000004U 75#define TC_CMR_TCCLKS_XC0 0x00000005U 76#define TC_CMR_TCCLKS_XC1 0x00000006U 77#define TC_CMR_TCCLKS_XC2 0x00000007U 78#define TC_CMR_TCCLKS_MCK_DIV_2 TC_CMR_TCCLKS_CLOCK1 79#define TC_CMR_TCCLKS_MCK_DIV_8 TC_CMR_TCCLKS_CLOCK2 80#define TC_CMR_TCCLKS_MCK_DIV_32 TC_CMR_TCCLKS_CLOCK3 81#define TC_CMR_TCCLKS_MCK_DIV_128 TC_CMR_TCCLKS_CLOCK4 82#define TC_CMR_TCCLKS_SLCK TC_CMR_TCCLKS_CLOCK5 83 84 85/* Channel Mode Register bits in capture mode: */ 86#define TC_CMR_LDRB 0x000C0000U 87#define TC_CMR_LDRB_SHIFT 18U 88#define TC_CMR_LDRB_NONE 0x00000000U 89#define TC_CMR_LDRB_RISING 0x00040000U 90#define TC_CMR_LDRB_FALLING 0x00080000U 91#define TC_CMR_LDRB_BOTH 0x000C0000U 92 93#define TC_CMR_LDRA 0x00030000U 94#define TC_CMR_LDRA_SHIFT 16U 95#define TC_CMR_LDRA_NONE 0x00000000U 96#define TC_CMR_LDRA_RISING 0x00010000U 97#define TC_CMR_LDRA_FALLING 0x00020000U 98#define TC_CMR_LDRA_BOTH 0x00030000U 99 100 101#define TC_CMR_CPCTRG 0x00004000U /* 1 = RC compare resets cntr */ 102#define TC_CMR_ABETRG 0x00000400U /* 1 = TIOA is ext trig */ 103 104#define TC_CMR_ETRGEDG 0x00000300U /* external trigger edge sel */ 105#define TC_CMR_ETRGEDG_SHIFT 8U 106#define TC_CMR_ETRGEDG_NONE 0x00000000U 107#define TC_CMR_ETRGEDG_RISING 0x00000100U 108#define TC_CMR_ETRGEDG_FALLING 0x00000200U 109#define TC_CMR_ETRGEDG_BOTH 0x00000300U 110 111#define TC_CMR_LDBDIS 0x00000080U /* 1 = disable counter after loading RB */ 112#define TC_CMR_LDBSTOP 0x00000040U /* 1 = stop counter after loading RB */ 113 114/* Channel Mode Register bits in Waveform mode: */ 115#define TC_CMR_BSWTRG 0xC0000000U /* Software Trigger Effect on TIOB */ 116#define TC_CMR_BSWTRG_NONE 0x00000000U 117#define TC_CMR_BSWTRG_SET 0x40000000U 118#define TC_CMR_BSWTRG_CLEAR 0x80000000U 119#define TC_CMR_BSWTRG_TOGGLE 0xC0000000U 120 121#define TC_CMR_BEEVT 0x30000000U /* External Event Effect on TIOB */ 122#define TC_CMR_BEEVT_NONE 0x00000000U 123#define TC_CMR_BEEVT_SET 0x10000000U 124#define TC_CMR_BEEVT_CLEAR 0x20000000U 125#define TC_CMR_BEEVT_TOGGLE 0x30000000U 126 127#define TC_CMR_BCPC 0x0C000000U /* RC Compare Effect on TIOB */ 128#define TC_CMR_BCPC_NONE 0x00000000U 129#define TC_CMR_BCPC_SET 0x04000000U 130#define TC_CMR_BCPC_CLEAR 0x08000000U 131#define TC_CMR_BCPC_TOGGLE 0x0C000000U 132 133#define TC_CMR_BCPB 0x03000000U /* RB Compare Effect on TIOB */ 134#define TC_CMR_BCPB_NONE 0x00000000U 135#define TC_CMR_BCPB_SET 0x01000000U 136#define TC_CMR_BCPB_CLEAR 0x02000000U 137#define TC_CMR_BCPB_TOGGLE 0x03000000U 138 139#define TC_CMR_ASWTRG 0x00C00000U /* Software Trigger Effect on TIOA: */ 140#define TC_CMR_ASWTRG_NONE 0x00000000U 141#define TC_CMR_ASWTRG_SET 0x00400000U 142#define TC_CMR_ASWTRG_CLEAR 0x00800000U 143#define TC_CMR_ASWTRG_TOGGLE 0x00C00000U 144 145#define TC_CMR_AEVT 0x00300000U 146#define TC_CMR_AEVT_NONE 0x00000000U 147#define TC_CMR_AEVT_SET 0x00100000U 148#define TC_CMR_AEVT_CLEAR 0x00200000U 149#define TC_CMR_AEVT_TOGGLE 0x00300000U 150 151#define TC_CMR_ACPC 0x000C0000U /* RC Compare Effect on TIOA: */ 152#define TC_CMR_ACPC_NONE 0x00000000U 153#define TC_CMR_ACPC_SET 0x00040000U 154#define TC_CMR_ACPC_CLEAR 0x00080000U 155#define TC_CMR_ACPC_TOGGLE 0x000C0000U 156 157#define TC_CMR_ACPA 0x00030000U /* RA Compare Effect on TIOA: */ 158#define TC_CMR_ACPA_NONE 0x00000000U 159#define TC_CMR_ACPA_SET 0x00010000U 160#define TC_CMR_ACPA_CLEAR 0x00020000U 161#define TC_CMR_ACPA_TOGGLE 0x00030000U 162 163#define TC_CMR_WAVSEL 0x00006000U /* Waveform selection */ 164#define TC_CMR_WAVSEL_UP 0x00000000U 165#define TC_CMR_WAVSEL_UPDOWN 0x00002000U 166#define TC_CMR_WAVSEL_UP_RC 0x00004000U 167#define TC_CMR_WAVSEL_UPDOWN_RC 0x00006000U 168 169#define TC_CMR_ENETRG 0x00001000U /* 1 = external event resets the cntr */ 170 171#define TC_CMR_EEVT 0x00000C00U /* External Event Sel */ 172#define TC_CMR_EEVT_TIOB 0x00000000U 173#define TC_CMR_EEVT_XC0 0x00000400U 174#define TC_CMR_EEVT_XC1 0x00000800U 175#define TC_CMR_EEVT_XC2 0x00000C00U 176 177 178#define TC_CMR_EEVTEDG 0x00000300U /* External Event Edge Sel */ 179#define TC_CMR_EEVTEDG_NONE 0x00000000U 180#define TC_CMR_EEVTEDG_RISING 0x00000100U 181#define TC_CMR_EEVTEDG_FALLING 0x00000200U 182#define TC_CMR_EEVTEDG_BOTH 0x00000300U 183 184#define TC_CMR_CPCDIS 0x00000080U /* 1 = RC compare disables cntr */ 185#define TC_CMR_CPCSTOP 0x00000040U /* 1 = RC compare stops cntr */ 186 187 188/* Channel Status Register bits: */ 189#define TC_SR_MTIOB 0x00040000U 190#define TC_SR_MTIOA 0x00020000U 191#define TC_SR_CLKSTA 0x00010000U 192 193#define TC_SR_ETRGS 0x80U 194#define TC_SR_LDRBS 0x40U 195#define TC_SR_LDRAS 0x20U 196#define TC_SR_CPCS 0x10U 197#define TC_SR_CPBS 0x08U 198#define TC_SR_CPAS 0x04U 199#define TC_SR_LOVRS 0x02U 200#define TC_SR_COVFS 0x01U 201 202 203/* timer registers: */ 204 205#define TC_BCR 0x00U /* Block Control Register */ 206#define TC_BMR 0x04U /* Block Mode Register */ 207 208/* Block Control Register bits: */ 209#define TC_BCR_SYNC 0x00000001U /* 1 = asserts the SYNC signal */ 210 211/* Block Mode Register bits: */ 212#define TC_BMR_TC2XC2S 0x30U /* External Clock Signal 2 Sel */ 213#define TC_BMR_TC2XC2S_SHIFT 4U 214#define TC_BMR_TC2XC2S_TCLK2 0x00U 215#define TC_BMR_TC2XC2S_TIOA0 0x20U 216#define TC_BMR_TC2XC2S_TIOA1 0x30U 217 218#define TC_BMR_TC1XC1S 0x0CU /* External Clock Signal 1 Sel */ 219#define TC_BMR_TC1XC1S_SHIFT 2U 220#define TC_BMR_TC1XC1S_TCLK1 0x00U 221#define TC_BMR_TC1XC1S_TIOA0 0x08U 222#define TC_BMR_TC1XC1S_TIOA2 0x0CU 223 224#define TC_BMR_TC0XC0S 0x03U /* External Clock Signal 0 Sel */ 225#define TC_BMR_TC0XC0S_SHIFT 0U 226#define TC_BMR_TC0XC0S_TCLK0 0x00U 227#define TC_BMR_TC0XC0S_TIOA1 0x02U 228#define TC_BMR_TC0XC0S_TIOA2 0x03U 229 230#endif /* !_AT91TCREG_H_ */ 231