1/*	$Id: at91pio.c,v 1.8 2021/08/07 16:18:43 thorpej Exp $	*/
2/*	$NetBSD: at91pio.c,v 1.8 2021/08/07 16:18:43 thorpej Exp $	*/
3
4/*
5 * Copyright (c) 2007 Embedtronics Oy. All rights reserved.
6 *
7 * Based on arch/arm/ep93xx/epgpio.c,
8 * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: at91pio.c,v 1.8 2021/08/07 16:18:43 thorpej Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/device.h>
39#include <sys/gpio.h>
40#include <sys/bus.h>
41#include <machine/intr.h>
42#include <dev/gpio/gpiovar.h>
43#include <arm/at91/at91var.h>
44#include <arm/at91/at91reg.h>
45#include <arm/at91/at91pioreg.h>
46#include <arm/at91/at91piovar.h>
47#include "gpio.h"
48#if NGPIO > 0
49#include <sys/gpio.h>
50#endif
51#include "locators.h"
52
53#ifdef AT91PIO_DEBUG
54int at91pio_debug = AT91PIO_DEBUG;
55#define DPRINTFN(n,x)	if (at91pio_debug>(n)) printf x;
56#else
57#define DPRINTFN(n,x)
58#endif
59
60#define	AT91PIO_NMAXPORTS	4
61#define	AT91PIO_NPINS		32
62
63struct intr_req {
64	int			(*ireq_func)(void *);
65	void			*ireq_arg;
66	int			ireq_ipl;
67};
68
69#define	PIO_READ(_sc, _reg)		bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg))
70#define	PIO_WRITE(_sc, _reg, _val)	bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg), (_val))
71
72struct at91pio_softc {
73	bus_space_tag_t		sc_iot;
74	bus_space_handle_t	sc_ioh;
75	int			sc_pid;
76#if NGPIO > 0
77	struct gpio_chipset_tag	gpio_chipset;
78	gpio_pin_t		pins[AT91PIO_NPINS];
79#endif
80	int			irq;
81	void			*ih;
82	struct intr_req		ireq[AT91PIO_NPINS];
83};
84
85static int at91pio_match(device_t, cfdata_t, void *);
86static void at91pio_attach(device_t, device_t, void *);
87
88#if NGPIO > 0
89static int at91piobus_print(void *, const char *);
90static int at91pio_pin_read(void *, int);
91static void at91pio_pin_write(void *, int, int);
92static void at91pio_pin_ctl(void *, int, int);
93#endif
94
95static int at91pio_search(device_t, cfdata_t, const int *, void *);
96static int at91pio_print(void *, const char *);
97
98static int at91pio_intr(void* arg);
99
100CFATTACH_DECL_NEW(at91pio, sizeof(struct at91pio_softc),
101	      at91pio_match, at91pio_attach, NULL, NULL);
102
103static struct at91pio_softc *at91pio_softc[AT91_PIO_COUNT];
104
105struct at91pio_softc *at91pio_sc(at91pio_port port)
106{
107	if (port < AT91_PIO_COUNT)
108		return at91pio_softc[port];
109	return NULL;
110}
111
112
113static int
114at91pio_match(device_t parent, cfdata_t match, void *aux)
115{
116	if (strcmp(match->cf_name, "at91pio") == 0)
117		return 2;
118	return 0;
119}
120
121static void
122at91pio_attach(device_t parent, device_t self, void *aux)
123{
124	struct at91pio_softc *sc = device_private(self);
125	struct at91bus_attach_args *sa = aux;
126#if NGPIO > 0
127	struct gpiobus_attach_args gba;
128	uint32_t psr, osr, pin;
129	int j, n;
130#endif
131	printf("\n");
132	sc->sc_iot = sa->sa_iot;
133	sc->sc_pid = sa->sa_pid;
134
135	if (bus_space_map(sa->sa_iot, sa->sa_addr,
136			  sa->sa_size, 0, &sc->sc_ioh)){
137		printf("%s: Cannot map registers", device_xname(self));
138		return;
139	}
140
141	/* save descriptor: */
142	at91pio_port p = at91_pio_port(sa->sa_pid);
143	if (p < AT91_PIO_COUNT && !at91pio_softc[p])
144		at91pio_softc[p] = sc;
145
146	/* make sure peripheral is enabled: */
147	at91_peripheral_clock(sc->sc_pid, 1);
148
149	/* initialize ports (disable interrupts) */
150	PIO_WRITE(sc, PIO_IDR, -1);
151
152#if NGPIO > 0
153	/* initialize and attach gpio(4) */
154	psr = PIO_READ(sc, PIO_PSR);	// only ports
155	osr = PIO_READ(sc, PIO_OSR);
156	pin = PIO_READ(sc, PIO_PDSR);
157	psr &= ~at91_gpio_mask(sc->sc_pid);
158	for (j = n = 0; j < AT91PIO_NPINS; j++) {
159		sc->pins[n].pin_num = j;
160		if (psr & (1 << j))
161			sc->pins[n].pin_caps = (GPIO_PIN_INPUT
162						| GPIO_PIN_OUTPUT
163						| GPIO_PIN_OPENDRAIN // @@@ not all pins
164						| GPIO_PIN_PUSHPULL
165						| GPIO_PIN_PULLUP);
166		else
167			sc->pins[n].pin_caps = 0;
168
169		if (osr & (1 << j))
170			sc->pins[n].pin_flags = GPIO_PIN_OUTPUT;
171		else
172			sc->pins[n].pin_flags = GPIO_PIN_INPUT;
173		if (pin & (1 << j))
174			sc->pins[n].pin_state = GPIO_PIN_HIGH;
175		else
176			sc->pins[n].pin_state = GPIO_PIN_LOW;
177		n++;
178	}
179	sc->gpio_chipset.gp_cookie = sc;
180	sc->gpio_chipset.gp_pin_read = at91pio_pin_read;
181	sc->gpio_chipset.gp_pin_write = at91pio_pin_write;
182	sc->gpio_chipset.gp_pin_ctl = at91pio_pin_ctl;
183	gba.gba_gc = &sc->gpio_chipset;
184	gba.gba_pins = sc->pins;
185	gba.gba_npins = n;
186	config_found(self, &gba, at91piobus_print,
187	    CFARGS(.iattr = "gpiobus"));
188#endif
189
190	/* attach device */
191	config_search(self, NULL,
192	    CFARGS(.search = at91pio_search,
193		   .iattr = "at91pio"));
194}
195
196#if NGPIO > 0
197static int
198at91piobus_print(void *aux, const char *name)
199{
200	struct gpiobus_attach_args *gba = aux;
201	struct at91pio_softc *sc = (struct at91pio_softc *)gba->gba_gc->gp_cookie;
202
203	gpiobus_print(aux, name);
204	aprint_normal(": port %s (mask %08"PRIX32")",
205		      at91_peripheral_name(sc->sc_pid),
206		      at91_gpio_mask(sc->sc_pid));
207
208	return (UNCONF);
209}
210#endif
211
212
213static int
214at91pio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
215{
216	struct at91pio_softc *sc = device_private(parent);
217	struct at91pio_attach_args paa;
218
219	paa.paa_sc = sc;
220	paa.paa_iot = sc->sc_iot;
221	paa.paa_pid = cf->cf_loc[AT91PIOCF_PID];
222	paa.paa_bit = cf->cf_loc[AT91PIOCF_BIT];
223
224	if (config_probe(parent, cf, &paa))
225		config_attach(parent, cf, &paa, at91pio_print, CFARGS_NONE);
226
227	return 0;
228}
229
230static int
231at91pio_print(void *aux, const char *name)
232{
233	struct at91pio_attach_args *paa = aux;
234
235	aprint_normal(":");
236	if (paa->paa_pid > -1)
237		aprint_normal(" port %s", at91_peripheral_name(paa->paa_pid));
238	if (paa->paa_bit > -1)
239		aprint_normal(" bit %d", paa->paa_bit);
240
241	return (UNCONF);
242}
243
244int
245at91pio_read(struct at91pio_softc *sc, int bit)
246{
247#if NGPIO > 0
248	sc->pins[bit].pin_caps = 0;
249#endif
250	return (PIO_READ(sc, PIO_PDSR) >> bit) & 1;
251}
252
253void
254at91pio_set(struct at91pio_softc *sc, int bit)
255{
256#if NGPIO > 0
257	sc->pins[bit].pin_caps = 0;
258#endif
259	PIO_WRITE(sc, PIO_SODR, (1U << bit));
260}
261
262void
263at91pio_clear(struct at91pio_softc *sc, int bit)
264{
265#if NGPIO > 0
266	sc->pins[bit].pin_caps = 0;
267#endif
268	PIO_WRITE(sc, PIO_CODR, (1U << bit));
269}
270
271void
272at91pio_in(struct at91pio_softc *sc, int bit)
273{
274#if NGPIO > 0
275	sc->pins[bit].pin_caps = 0;
276#endif
277	PIO_WRITE(sc, PIO_ODR, (1U << bit));
278}
279
280void
281at91pio_out(struct at91pio_softc *sc, int bit)
282{
283#if NGPIO > 0
284	sc->pins[bit].pin_caps = 0;
285#endif
286	PIO_WRITE(sc, PIO_OER, (1U << bit));
287}
288
289void at91pio_per(struct at91pio_softc *sc, int bit, int perab)
290{
291#if NGPIO > 0
292	sc->pins[bit].pin_caps = 0;
293#endif
294	switch (perab) {
295	case -1:
296		PIO_WRITE(sc, PIO_PER, (1U << bit));
297		break;
298	case 0:
299		PIO_WRITE(sc, PIO_ASR, (1U << bit));
300		PIO_WRITE(sc, PIO_PDR, (1U << bit));
301		break;
302	case 1:
303		PIO_WRITE(sc, PIO_BSR, (1U << bit));
304		PIO_WRITE(sc, PIO_PDR, (1U << bit));
305		break;
306	default:
307		panic("%s: perab is invalid: %i", __FUNCTION__, perab);
308		break;
309	}
310}
311
312void *
313at91pio_intr_establish(struct at91pio_softc *sc, int bit,
314			 int ipl, int (*ireq_func)(void *), void *arg)
315{
316	struct intr_req *ireq;
317
318	DPRINTFN(1, ("at91pio_intr_establish: port=%s, bit=%d\n", at91_peripheral_name(sc->sc_pid), bit));
319
320	if (bit < 0 || bit >= AT91PIO_NPINS)
321		return 0;
322
323	ireq = &sc->ireq[bit];
324
325	if (ireq->ireq_func)	/* already used */
326		return 0;
327
328	ireq->ireq_func = ireq_func;
329	ireq->ireq_arg = arg;
330	ireq->ireq_ipl = ipl;
331
332	PIO_WRITE(sc, PIO_IDR, (1U << bit));	/* disable interrupt for now */
333	at91pio_in(sc, bit);			/* make sure pin is input */
334#if NGPIO > 0
335	sc->pins[bit].pin_caps = 0;
336#endif
337#if 0
338	if (flag & EDGE_TRIGGER)
339		at91pio_bit_set(sc, sc->xinttype1, bit);
340	else	/* LEVEL_SENSE */
341		at91pio_bit_clear(sc, sc->xinttype1, bit);
342	if (flag & RISING_EDGE)	/* or HIGH_LEVEL */
343		at91pio_bit_set(sc, sc->xinttype2, bit);
344	else	/* FALLING_EDGE or LOW_LEVEL */
345		at91pio_bit_clear(sc, sc->xinttype2, bit);
346	if (flag & DEBOUNCE)
347		PIO_WRITE(sc, PIO_IFER, (1U << bit));
348	else
349		PIO_WRITE(sc, PIO_IFDR, (1U << bit));
350#endif
351
352	if (!sc->ih) {
353		// use IPL_BIO because we want lowest possible priority as
354		// we really don't know what priority is going to be used by
355		// the caller.. this is not really optimal but tell me a
356		// better way
357		sc->ih = at91_intr_establish(sc->sc_pid, IPL_BIO, INTR_HIGH_LEVEL,
358					      at91pio_intr, sc);
359	}
360
361	//(void)PIO_READ(sc, PIO_ISR);	// clear interrupts
362	PIO_WRITE(sc, PIO_IER, (1U << bit));	// enable interrupt
363
364	return sc->ih;
365}
366
367void
368at91pio_intr_disestablish(struct at91pio_softc *sc, int bit, void *cookie)
369{
370	struct intr_req *ireq;
371	int i;
372
373	DPRINTFN(1, ("at91pio_intr_disestablish: port=%s, bit=%d\n", at91_peripheral_name(sc->sc_pid), bit));
374
375	if (bit < 0 || bit >= AT91PIO_NPINS)
376		return;
377
378if (cookie != sc->ih)
379		return;
380
381	ireq = &sc->ireq[bit];
382
383	if (!ireq->ireq_func)
384		return;
385
386	PIO_WRITE(sc, PIO_IDR, (1U << bit));
387	ireq->ireq_func = 0;
388	ireq->ireq_arg = 0;
389
390	for (i = 0; i < AT91PIO_NPINS; i++) {
391		if (sc->ireq[i].ireq_func)
392			break;
393	}
394
395	if (i >= AT91PIO_NPINS) {
396		at91_intr_disestablish(sc->ih);
397		sc->ih = 0;
398	}
399}
400
401static int
402at91pio_intr(void *arg)
403{
404	struct at91pio_softc *sc = arg;
405	int bit;
406	uint32_t isr;
407
408	isr = (PIO_READ(sc, PIO_ISR) & PIO_READ(sc, PIO_IMR));
409	if (!isr)
410		return 0;
411
412	do {
413		bit = ffs(isr) - 1;
414		isr &= ~(1U << bit);
415#ifdef	DIAGNOSTIC
416		if (bit < 0)
417			panic("%s: isr is zero (0x%X)", __FUNCTION__, isr);
418#endif
419		if (sc->ireq[bit].ireq_func) {
420			int s = _splraise(sc->ireq[bit].ireq_ipl);
421			(*sc->ireq[bit].ireq_func)(sc->ireq[bit].ireq_arg);
422			splx(s);
423		}
424	} while (isr);
425
426	return 1;
427}
428
429
430#if NGPIO > 0
431static int
432at91pio_pin_read(void *arg, int pin)
433{
434	struct at91pio_softc *sc = arg;
435
436	pin %= AT91PIO_NPINS;
437	if (!sc->pins[pin].pin_caps)
438		return 0; /* EBUSY? */
439
440	return (PIO_READ(sc, PIO_PDSR) >> pin) & 1;
441}
442
443static void
444at91pio_pin_write(void *arg, int pin, int val)
445{
446	struct at91pio_softc *sc = arg;
447
448	pin %= AT91PIO_NPINS;
449	if (!sc->pins[pin].pin_caps)
450		return;
451
452	if (val)
453		PIO_WRITE(sc, PIO_SODR, (1U << pin));
454	else
455		PIO_WRITE(sc, PIO_CODR, (1U << pin));
456}
457
458static void
459at91pio_pin_ctl(void *arg, int pin, int flags)
460{
461	struct at91pio_softc *sc = arg;
462
463	pin %= AT91PIO_NPINS;
464	if (!sc->pins[pin].pin_caps)
465		return;
466
467	if (flags & GPIO_PIN_INPUT)
468		PIO_WRITE(sc, PIO_ODR, (1U << pin));
469	else if (flags & GPIO_PIN_OUTPUT)
470		PIO_WRITE(sc, PIO_OER, (1U << pin));
471
472	if (flags & GPIO_PIN_OPENDRAIN)
473		PIO_WRITE(sc, PIO_MDER, (1U << pin));
474	else if (flags & GPIO_PIN_PUSHPULL)
475		PIO_WRITE(sc, PIO_MDDR, (1U << pin));
476
477	if (flags & GPIO_PIN_PULLUP)
478		PIO_WRITE(sc, PIO_PUER, (1U << pin));
479	else
480		PIO_WRITE(sc, PIO_PUDR, (1U << pin));
481}
482#endif
483
484