cortex_pmc.c revision 1.7 
1/*	$NetBSD: cortex_pmc.c,v 1.7 2019/01/27 02:08:37 pgoyette Exp $	*/
2
3/* Copyright (c) 2007 Microsoft
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by Microsoft
17 *
18 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31
32/*
33 * support for ARM cortex Performance Monitor Counters
34 * based on arm11_pmc.c
35 */
36
37#include <sys/cdefs.h>
38/* __KERNEL_RCSID(0, "$NetBSD: cortex_pmc.c,v 1.7 2019/01/27 02:08:37 pgoyette Exp $"); */
39#include <sys/types.h>
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/time.h>
44#include <sys/timetc.h>
45
46#include <dev/clock_subr.h>
47
48#include <uvm/uvm_extern.h>
49
50#include <arm/armreg.h>
51#include <arm/cpufunc.h>
52#include <arm/arm32/machdep.h>
53
54#ifndef CORTEX_PMC_CCNT_HZ
55# define CORTEX_PMC_CCNT_HZ	400000000	/* 400MHz */
56#endif
57
58#define COUNTS_PER_USEC	(curcpu()->ci_data.cpu_cc_freq / (1000*1000))
59
60static const uint32_t counts_per_wrap = ~0UL - 1;
61
62/*
63 * enable the PMC CCNT for delay()
64 */
65void
66cortex_pmc_ccnt_init(void)
67{
68	if (curcpu()->ci_data.cpu_cc_freq == 0) {
69		curcpu()->ci_data.cpu_cc_freq = CORTEX_PMC_CCNT_HZ;
70	}
71}
72
73/*
74 * delay - for "at least" arg usec
75 *
76 *	NOTE: at 400MHz we are restricted to (uint32_t)~0 "counts"
77 *	if this is a problem, accumulate counts in LL vars
78 */
79void
80delay(u_int arg)
81{
82	uint32_t ctrl;
83	uint32_t cur;
84	uint32_t last;
85	uint32_t delta = 0;
86	uint32_t usecs = 0;
87	const uint32_t counts_per_usec = COUNTS_PER_USEC;
88	const uint32_t delay_arg_limit = ~0UL / counts_per_usec; /* about 10 sec */
89
90	if (arg > delay_arg_limit)
91		panic("%s: arg %u overflow, limit is %u usec\n",
92		    __func__, arg, delay_arg_limit);
93
94	last = armreg_pmccntr_read();
95	delta = usecs = 0;
96	while (arg > usecs) {
97		cur = armreg_pmccntr_read();
98
99		/*
100		 * overflow flag is moved to a separate register
101		 * and is not read from PMC Control Register
102		 */
103		ctrl = armreg_pmovsr_read();
104		if (ctrl & CORTEX_CNTOFL_C) {
105			/*
106			 * Reset overflow flag for cycle counter in overflow
107			 * register
108			 */
109			armreg_pmovsr_write(CORTEX_CNTOFL_C);
110			delta += (cur + (counts_per_wrap - last));
111		} else {
112			delta += (cur - last);
113		}
114		last = cur;
115		if (delta >= counts_per_usec) {
116			usecs += delta / counts_per_usec;
117			delta %= counts_per_usec;
118		}
119	}
120}
121