1/* $NetBSD: apple_iic.c,v 1.1 2022/05/10 08:05:32 skrll Exp $ */ 2/* $OpenBSD: apliic.c,v 1.3 2022/02/14 14:55:53 kettenis Exp $ */ 3 4/*- 5 * Copyright (c) 2022 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Nick Hudson 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 2021 Patrick Wildt <patrick@blueri.se> 35 * 36 * Permission to use, copy, modify, and distribute this software for any 37 * purpose with or without fee is hereby granted, provided that the above 38 * copyright notice and this permission notice appear in all copies. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 47 */ 48 49#include <sys/param.h> 50 51#include <sys/bus.h> 52#include <sys/device.h> 53 54#include <dev/i2c/i2cvar.h> 55 56#include <dev/fdt/fdtvar.h> 57 58/* Registers. */ 59#define I2C_MTXFIFO 0x00 60#define I2C_MTXFIFO_DATA_MASK __BITS(7,0) 61#define I2C_MTXFIFO_START __BIT(8) 62#define I2C_MTXFIFO_STOP __BIT(9) 63#define I2C_MTXFIFO_READ __BIT(10) 64#define I2C_MRXFIFO 0x04 65#define I2C_MRXFIFO_DATA_MASK __BITS(7,0) 66#define I2C_MRXFIFO_EMPTY __BIT(8) 67#define I2C_SMSTA 0x14 68#define I2C_SMSTA_MTN __BIT(21) 69#define I2C_SMSTA_XEN __BIT(27) 70#define I2C_SMSTA_XBUSY __BIT(28) 71#define I2C_CTL 0x1c 72#define I2C_CTL_CLK_MASK __BITS(7,0) 73#define I2C_CTL_MTR __BIT(9) 74#define I2C_CTL_MRR __BIT(10) 75#define I2C_CTL_EN __BIT(11) 76#define I2C_REV 0x28 77 78#define IIC_READ(sc, reg) \ 79 (bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))) 80#define IIC_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82#define HSET4(sc, reg, bits) \ 83 IIC_WRITE((sc), (reg), IIC_READ((sc), (reg)) | (bits)) 84#define HCLR4(sc, reg, bits) \ 85 IIC_WRITE((sc), (reg), IIC_READ((sc), (reg)) & ~(bits)) 86 87struct apple_iic_softc { 88 device_t sc_dev; 89 bus_space_tag_t sc_bst; 90 bus_space_handle_t sc_bsh; 91 92 struct clk * sc_clk; 93 int sc_hwrev; 94 uint32_t sc_clkdiv; 95 struct i2c_controller sc_i2c; 96}; 97 98 99static int 100apple_iic_acquire_bus(void *cookie, int flags) 101{ 102 return 0; 103} 104 105static void 106apple_iic_release_bus(void *cookie, int flags) 107{ 108} 109 110static int 111apple_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 112 size_t cmdlen, void *buf, size_t buflen, int flags) 113{ 114 struct apple_iic_softc *sc = cookie; 115 const uint8_t * const cmdbytes = cmd; 116 uint8_t * const bufbytes = buf; 117 uint32_t reg; 118 int i; 119 120 if (!I2C_OP_STOP_P(op)) 121 return EINVAL; 122 123 IIC_WRITE(sc, I2C_SMSTA, 0xffffffff); 124 125 if (cmdlen > 0) { 126 IIC_WRITE(sc, I2C_MTXFIFO, I2C_MTXFIFO_START | addr << 1); 127 for (i = 0; i < cmdlen - 1; i++) 128 IIC_WRITE(sc, I2C_MTXFIFO, cmdbytes[i]); 129 IIC_WRITE(sc, I2C_MTXFIFO, cmdbytes[cmdlen - 1] | 130 (buflen == 0 ? I2C_MTXFIFO_STOP : 0)); 131 } 132 133 if (buflen == 0) 134 return 0; 135 136 if (I2C_OP_READ_P(op)) { 137 IIC_WRITE(sc, I2C_MTXFIFO, I2C_MTXFIFO_START | addr << 1 | 1); 138 IIC_WRITE(sc, I2C_MTXFIFO, I2C_MTXFIFO_READ | buflen | 139 I2C_MTXFIFO_STOP); 140 for (i = 10; i > 0; i--) { 141 delay(1000); 142 reg = IIC_READ(sc, I2C_SMSTA); 143 if (reg & I2C_SMSTA_XEN) 144 break; 145 } 146 if (reg & I2C_SMSTA_MTN) 147 return ENXIO; 148 if (i == 0) 149 return ETIMEDOUT; 150 IIC_WRITE(sc, I2C_SMSTA, I2C_SMSTA_XEN); 151 for (i = 0; i < buflen; i++) { 152 reg = IIC_READ(sc, I2C_MRXFIFO); 153 if (reg & I2C_MRXFIFO_EMPTY) 154 return EIO; 155 bufbytes[i] = reg & I2C_MRXFIFO_DATA_MASK; 156 } 157 } else { 158 if (cmdlen == 0) 159 IIC_WRITE(sc, I2C_MTXFIFO, I2C_MTXFIFO_START | addr << 1); 160 for (i = 0; i < buflen - 1; i++) 161 IIC_WRITE(sc, I2C_MTXFIFO, bufbytes[i]); 162 IIC_WRITE(sc, I2C_MTXFIFO, bufbytes[buflen - 1] | 163 I2C_MTXFIFO_STOP); 164 } 165 166 return 0; 167} 168 169 170static const struct device_compatible_entry compat_data[] = { 171 { .compat = "apple,i2c" }, 172 DEVICE_COMPAT_EOL 173}; 174 175static int 176apple_iic_match(device_t parent, cfdata_t cf, void *aux) 177{ 178 struct fdt_attach_args * const faa = aux; 179 180 return of_compatible_match(faa->faa_phandle, compat_data); 181} 182 183static void 184apple_iic_attach(device_t parent, device_t self, void *aux) 185{ 186 struct apple_iic_softc * const sc = device_private(self); 187 struct fdt_attach_args * const faa = aux; 188 const int phandle = faa->faa_phandle; 189 uint32_t clock_speed, bus_speed; 190 bus_addr_t addr; 191 bus_size_t size; 192 193 sc->sc_dev = self; 194 sc->sc_bst = faa->faa_bst; 195 196 int error = fdtbus_get_reg(phandle, 0, &addr, &size); 197 if (error) { 198 aprint_error(": unable to get device registers\n"); 199 return; 200 } 201 202 /* Enable clock */ 203 sc->sc_clk = fdtbus_clock_get_index(phandle, 0); 204 if (sc->sc_clk == NULL) { 205 aprint_error(": couldn't acquire clock\n"); 206 return; 207 } 208 209 if (clk_enable(sc->sc_clk) != 0) { 210 aprint_error(": failed to enable clock\n"); 211 return; 212 } 213 214 clock_speed = clk_get_rate(sc->sc_clk); 215 216 if (of_getprop_uint32(phandle, "clock-frequency", 217 &bus_speed) != 0) { 218 bus_speed = 100000; 219 } 220 bus_speed *= 16; 221 222 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh)) { 223 aprint_error(": unable to map device\n"); 224 return; 225 } 226 227 aprint_naive("\n"); 228 aprint_normal(": Apple I2C\n"); 229 230 sc->sc_clkdiv = howmany(clock_speed, bus_speed); 231 KASSERT(sc->sc_clkdiv <= __SHIFTOUT_MASK(I2C_CTL_CLK_MASK)); 232 233 sc->sc_hwrev = IIC_READ(sc, I2C_REV); 234 235 IIC_WRITE(sc, I2C_CTL, 236 __SHIFTIN(sc->sc_clkdiv, I2C_CTL_CLK_MASK) | 237 I2C_CTL_MTR | I2C_CTL_MRR | 238 (sc->sc_hwrev >= 6 ? I2C_CTL_EN : 0)); 239 240 iic_tag_init(&sc->sc_i2c); 241 sc->sc_i2c.ic_cookie = sc; 242 sc->sc_i2c.ic_acquire_bus = apple_iic_acquire_bus; 243 sc->sc_i2c.ic_release_bus = apple_iic_release_bus; 244 sc->sc_i2c.ic_exec = apple_iic_exec; 245 246 fdtbus_register_i2c_controller(&sc->sc_i2c, phandle); 247 248 fdtbus_attach_i2cbus(self, phandle, &sc->sc_i2c, iicbus_print); 249} 250 251 252CFATTACH_DECL_NEW(apple_iic, sizeof(struct apple_iic_softc), 253 apple_iic_match, apple_iic_attach, NULL, NULL); 254