mesongx_wdt.c revision 1.2 
1/* $NetBSD: mesongx_wdt.c,v 1.2 2021/01/27 03:10:18 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: mesongx_wdt.c,v 1.2 2021/01/27 03:10:18 thorpej Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/cpu.h>
35#include <sys/device.h>
36#include <sys/wdog.h>
37
38#include <dev/sysmon/sysmonvar.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	CBUS_REG(x)		((x) << 2)
43
44#define	WATCHDOG_CNTL		CBUS_REG(0)
45#define	 CNTL_CLK_DIV_EN		__BIT(25)
46#define	 CNTL_CLK_EN			__BIT(24)
47#define	 CNTL_SYS_RESET_N_EN		__BIT(21)
48#define	 CNTL_WATCHDOG_EN		__BIT(18)
49#define	 CNTL_CLK_DIV_TCNT		__BITS(17,0)
50#define	WATCHDOG_CNTL1		CBUS_REG(1)
51#define	WATCHDOG_TCNT		CBUS_REG(2)
52#define	WATCHDOG_RESET		CBUS_REG(3)
53
54#define	WATCHDOG_PERIOD_DEFAULT		8
55#define	WATCHDOG_PERIOD_MAX		8
56
57static const struct device_compatible_entry compat_data[] = {
58	{ .compat = "amlogic,meson-gx-wdt" },
59	DEVICE_COMPAT_EOL
60};
61
62struct mesongx_wdt_softc {
63	device_t		sc_dev;
64	bus_space_tag_t		sc_bst;
65	bus_space_handle_t	sc_bsh;
66
67	struct sysmon_wdog	sc_wdog;
68	u_int			sc_rate;
69};
70
71#define	WDT_READ(sc, reg)		\
72	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
73#define	WDT_WRITE(sc, reg, val)	\
74	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
75
76static int
77mesongx_wdt_setmode(struct sysmon_wdog *smw)
78{
79	struct mesongx_wdt_softc * const sc = smw->smw_cookie;
80
81	if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
82		WDT_WRITE(sc, WATCHDOG_CNTL, 0);
83		return 0;
84	}
85
86	if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
87		sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
88	} else if (smw->smw_period == 0 ||
89		   smw->smw_period > WATCHDOG_PERIOD_MAX) {
90		return EINVAL;
91	} else {
92		sc->sc_wdog.smw_period = smw->smw_period;
93	}
94
95	const u_int tcnt = sc->sc_rate / 1000;
96
97	WDT_WRITE(sc, WATCHDOG_CNTL, 0);
98	WDT_WRITE(sc, WATCHDOG_RESET, 0);
99	WDT_WRITE(sc, WATCHDOG_TCNT, sc->sc_wdog.smw_period * 1000);
100	WDT_WRITE(sc, WATCHDOG_CNTL,
101	    __SHIFTIN(tcnt, CNTL_CLK_DIV_TCNT) |
102	    CNTL_CLK_DIV_EN | CNTL_CLK_EN |
103	    CNTL_SYS_RESET_N_EN | CNTL_WATCHDOG_EN);
104
105	return 0;
106}
107
108static int
109mesongx_wdt_tickle(struct sysmon_wdog *smw)
110{
111	struct mesongx_wdt_softc * const sc = smw->smw_cookie;
112
113	WDT_WRITE(sc, WATCHDOG_RESET, 0);
114
115	return 0;
116}
117
118static int
119mesongx_wdt_match(device_t parent, cfdata_t cf, void *aux)
120{
121	struct fdt_attach_args * const faa = aux;
122
123	return of_compatible_match(faa->faa_phandle, compat_data);
124}
125
126static void
127mesongx_wdt_attach(device_t parent, device_t self, void *aux)
128{
129	struct mesongx_wdt_softc * const sc = device_private(self);
130	struct fdt_attach_args * const faa = aux;
131	const int phandle = faa->faa_phandle;
132	struct clk *clk;
133	bus_addr_t addr;
134	bus_size_t size;
135
136	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
137		aprint_error(": couldn't get registers\n");
138		return;
139	}
140
141	sc->sc_dev = self;
142	sc->sc_bst = faa->faa_bst;
143	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
144		aprint_error(": couldn't map registers\n");
145		return;
146	}
147
148	aprint_naive("\n");
149	aprint_normal(": EE-watchdog\n");
150
151	clk = fdtbus_clock_get_index(phandle, 0);
152	if (clk != NULL)
153		sc->sc_rate = clk_get_rate(clk);
154	else {
155		aprint_error_dev(self, "WARNING: couldn't get xtal clock, assuming 24 MHz\n");
156		sc->sc_rate = 24000000;
157	}
158
159	/* Disable watchdog */
160	WDT_WRITE(sc, WATCHDOG_CNTL, 0);
161
162	/* Register watchdog */
163	sc->sc_wdog.smw_name = "EE-watchdog";
164	sc->sc_wdog.smw_setmode = mesongx_wdt_setmode;
165	sc->sc_wdog.smw_tickle = mesongx_wdt_tickle;
166	sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
167	sc->sc_wdog.smw_cookie = sc;
168	sysmon_wdog_register(&sc->sc_wdog);
169}
170
171CFATTACH_DECL_NEW(mesongx_wdt, sizeof(struct mesongx_wdt_softc),
172    mesongx_wdt_match, mesongx_wdt_attach, NULL, NULL);
173