acpi_pci_layerscape_gen4.c revision 1.1
1/* $NetBSD: acpi_pci_layerscape_gen4.c,v 1.1 2020/02/01 13:26:43 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill@invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * NXP Layerscape PCIe Gen4 controller (not ECAM compliant) 34 */ 35 36#include <sys/cdefs.h> 37__KERNEL_RCSID(0, "$NetBSD: acpi_pci_layerscape_gen4.c,v 1.1 2020/02/01 13:26:43 jmcneill Exp $"); 38 39#include <sys/param.h> 40#include <sys/bus.h> 41#include <sys/device.h> 42#include <sys/intr.h> 43#include <sys/systm.h> 44#include <sys/kernel.h> 45#include <sys/extent.h> 46#include <sys/kmem.h> 47#include <sys/mutex.h> 48 49#include <machine/cpu.h> 50 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pcivar.h> 53#include <dev/pci/pciconf.h> 54 55#include <dev/acpi/acpivar.h> 56#include <dev/acpi/acpi_pci.h> 57#include <dev/acpi/acpi_mcfg.h> 58 59#include <arm/acpi/acpi_pci_machdep.h> 60 61#define PAB_CTRL 0x808 62#define PAB_CTRL_PAGE_SEL __BITS(18,13) 63#define PAB_AXI_AMAP_PEX_WIN_L(x) (0xba8 + 0x10 * (x)) 64#define PAB_AXI_AMAP_PEX_WIN_H(x) (0xbac + 0x10 * (x)) 65#define INDIRECT_ADDR_BOUNDARY 0xc00 66 67#define LUT_BASE 0x80000 68#define LUT_GCR 0x28 69#define LUT_GCR_RRE __BIT(0) 70 71#define REG_TO_PAGE_INDEX(reg) (((reg) >> 10) & 0x3ff) 72#define REG_TO_PAGE_ADDR(reg) (((reg) & 0x3ff) | INDIRECT_ADDR_BOUNDARY) 73 74#define PAB_TARGET_BUS(b) ((b) << 24) 75#define PAB_TARGET_DEV(d) ((d) << 19) 76#define PAB_TARGET_FUNC(f) ((f) << 16) 77 78struct acpi_pci_layerscape_gen4 { 79 bus_space_tag_t bst; 80 bus_space_handle_t bsh; 81 uint8_t rev; 82 kmutex_t lock; 83}; 84 85static void 86acpi_pci_layerscape_gen4_ccsr_setpage(struct acpi_pci_layerscape_gen4 *pcie, u_int page_index) 87{ 88 uint32_t val; 89 90 val = bus_space_read_4(pcie->bst, pcie->bsh, PAB_CTRL); 91 val &= ~PAB_CTRL_PAGE_SEL; 92 val |= __SHIFTIN(page_index, PAB_CTRL_PAGE_SEL); 93 bus_space_write_4(pcie->bst, pcie->bsh, PAB_CTRL, val); 94} 95 96static uint32_t 97acpi_pci_layerscape_gen4_ccsr_read4(struct acpi_pci_layerscape_gen4 *pcie, bus_size_t reg) 98{ 99 const bool indirect = reg >= INDIRECT_ADDR_BOUNDARY; 100 const u_int page_index = indirect ? REG_TO_PAGE_INDEX(reg) : 0; 101 const bus_size_t page_addr = indirect ? REG_TO_PAGE_ADDR(reg) : reg; 102 103 acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index); 104 return bus_space_read_4(pcie->bst, pcie->bsh, page_addr); 105} 106 107static void 108acpi_pci_layerscape_gen4_ccsr_write4(struct acpi_pci_layerscape_gen4 *pcie, 109 bus_size_t reg, pcireg_t data) 110{ 111 const bool indirect = reg >= INDIRECT_ADDR_BOUNDARY; 112 const u_int page_index = indirect ? REG_TO_PAGE_INDEX(reg) : 0; 113 const bus_size_t page_addr = indirect ? REG_TO_PAGE_ADDR(reg) : reg; 114 115 acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index); 116 bus_space_write_4(pcie->bst, pcie->bsh, page_addr, data); 117} 118 119static void 120acpi_pci_layerscape_gen4_select_target(struct acpi_pci_layerscape_gen4 *pcie, 121 pci_chipset_tag_t pc, pcitag_t tag) 122{ 123 struct acpi_pci_context *ap = pc->pc_conf_v; 124 int b, d, f; 125 126 pci_decompose_tag(pc, tag, &b, &d, &f); 127 128 const uint32_t target = PAB_TARGET_BUS(b - ap->ap_bus) | 129 PAB_TARGET_DEV(d) | PAB_TARGET_FUNC(f); 130 131 acpi_pci_layerscape_gen4_ccsr_write4(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target); 132 acpi_pci_layerscape_gen4_ccsr_write4(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0); 133} 134 135static bool 136acpi_pci_layerscape_gen4_is_tag_okay(pci_chipset_tag_t pc, pcitag_t tag) 137{ 138 struct acpi_pci_context *ap = pc->pc_conf_v; 139 int b, d, f; 140 141 pci_decompose_tag(pc, tag, &b, &d, &f); 142 143 if (b <= ap->ap_bus + 1 && d > 0) 144 return false; 145 146 return true; 147} 148 149static int 150acpi_pci_layerscape_gen4_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data) 151{ 152 struct acpi_pci_context *ap = pc->pc_conf_v; 153 struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv; 154 int b, d, f; 155 int error; 156 157 pci_decompose_tag(pc, tag, &b, &d, &f); 158 159 if (!acpi_pci_layerscape_gen4_is_tag_okay(pc, tag)) { 160 *data = -1; 161 return EINVAL; 162 } 163 164 mutex_enter(&pcie->lock); 165 166 if (pcie->rev == 0x10 && reg == PCI_ID_REG) 167 bus_space_write_4(pcie->bst, pcie->bsh, LUT_BASE + LUT_GCR, 0); 168 169 if (b == ap->ap_bus) { 170 *data = acpi_pci_layerscape_gen4_ccsr_read4(pcie, reg); 171 error = 0; 172 } else { 173 acpi_pci_layerscape_gen4_select_target(pcie, pc, tag); 174 error = acpimcfg_conf_read(pc, pci_make_tag(pc, 0, 0, 0), reg, data); 175 } 176 177 if (pcie->rev == 0x10 && reg == PCI_ID_REG) 178 bus_space_write_4(pcie->bst, pcie->bsh, LUT_BASE + LUT_GCR, LUT_GCR_RRE); 179 180 mutex_exit(&pcie->lock); 181 182 return error; 183} 184 185static int 186acpi_pci_layerscape_gen4_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 187{ 188 struct acpi_pci_context *ap = pc->pc_conf_v; 189 struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv; 190 int b, d, f; 191 int error; 192 193 pci_decompose_tag(pc, tag, &b, &d, &f); 194 195 if (!acpi_pci_layerscape_gen4_is_tag_okay(pc, tag)) 196 return EINVAL; 197 198 mutex_enter(&pcie->lock); 199 200 if (b == ap->ap_bus) { 201 acpi_pci_layerscape_gen4_ccsr_write4(pcie, reg, data); 202 error = 0; 203 } else { 204 acpi_pci_layerscape_gen4_select_target(pcie, pc, tag); 205 error = acpimcfg_conf_write(pc, pci_make_tag(pc, 0, 0, 0), reg, data); 206 } 207 208 mutex_exit(&pcie->lock); 209 210 return error; 211} 212 213static ACPI_STATUS 214acpi_pci_layerscape_gen4_map(ACPI_HANDLE handle, UINT32 level, void *ctx, void **retval) 215{ 216 struct acpi_pci_context *ap = ctx; 217 struct acpi_resources res; 218 struct acpi_mem *mem; 219 struct acpi_pci_layerscape_gen4 *pcie; 220 bus_space_handle_t bsh; 221 ACPI_HANDLE parent; 222 ACPI_INTEGER seg; 223 ACPI_STATUS rv; 224 int error; 225 226 rv = AcpiGetParent(handle, &parent); 227 if (ACPI_FAILURE(rv)) 228 return rv; 229 rv = acpi_eval_integer(parent, "_SEG", &seg); 230 if (ACPI_FAILURE(rv)) 231 seg = 0; 232 if (ap->ap_seg != seg) 233 return AE_OK; 234 235 rv = acpi_resource_parse(ap->ap_dev, handle, "_CRS", &res, &acpi_resource_parse_ops_quiet); 236 if (ACPI_FAILURE(rv)) 237 return rv; 238 239 mem = acpi_res_mem(&res, 0); 240 if (mem == NULL) { 241 acpi_resource_cleanup(&res); 242 return AE_NOT_FOUND; 243 } 244 245 error = bus_space_map(ap->ap_bst, mem->ar_base, mem->ar_length, 246 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &bsh); 247 if (error != 0) 248 return AE_NO_MEMORY; 249 250 pcie = kmem_alloc(sizeof(*pcie), KM_SLEEP); 251 pcie->bst = ap->ap_bst; 252 pcie->bsh = bsh; 253 mutex_init(&pcie->lock, MUTEX_DEFAULT, IPL_HIGH); 254 255 const pcireg_t cr = bus_space_read_4(pcie->bst, pcie->bsh, PCI_CLASS_REG); 256 pcie->rev = PCI_REVISION(cr); 257 258 ap->ap_conf_read = acpi_pci_layerscape_gen4_conf_read; 259 ap->ap_conf_write = acpi_pci_layerscape_gen4_conf_write; 260 ap->ap_conf_priv = pcie; 261 262 aprint_verbose_dev(ap->ap_dev, 263 "PCIe segment %lu: Layerscape Gen4 rev. %#x found at %#lx-%#lx\n", 264 seg, pcie->rev, mem->ar_base, mem->ar_base + mem->ar_length - 1); 265 266 return AE_CTRL_TERMINATE; 267} 268 269void 270acpi_pci_layerscape_gen4_init(struct acpi_pci_context *ap) 271{ 272 ACPI_STATUS rv; 273 274 rv = AcpiGetDevices(__UNCONST("NXP0016"), acpi_pci_layerscape_gen4_map, ap, NULL); 275 if (ACPI_FAILURE(rv)) 276 return; 277} 278