1/*	$NetBSD: jazzdmatlbreg.h,v 1.5 2023/06/25 15:36:11 andvar Exp $	*/
2/*	$OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $	*/
3
4/*
5 * Copyright (c) 1996 Per Fogelstrom
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *      This product includes software developed by Per Fogelstrom.
19 * 4. The name of the author may not be used to endorse or promote products
20 *    derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 *	The R4030 system has four DMA channels capable of scatter/gather
36 *	and full memory addressing. The maximum transfer length is 1Mb.
37 *	DMA snopes the L2 cache so no precaution is required. However
38 *	if L1 cache is cached 'write back' the processor is responsible
39 *	for flushing/invalidating it.
40 *
41 *	The DMA mapper has up to 4096 page descriptors.
42 */
43
44/* XXX */
45#define	PICA_TL_BASE		0xa0180000	/* Base of tl register area */
46#define JAZZ_DMATLB_SIZE	0x00008000	/* Size of tl register area */
47
48#define JAZZ_DMATLBREG_MAP	0x00		/* DMA transl. table base */
49#define JAZZ_DMATLBREG_LIMIT	0x08		/* DMA transl. table limit */
50#define JAZZ_DMATLBREG_IVALID	0x10		/* DMA transl. cache inval */
51#define JAZZ_DMATLB_REGSIZE	0x18		/* size of bus_space region */
52
53#define JAZZ_DMA_PAGE_SIZE	0x00001000		/* Address page size */
54#define JAZZ_DMA_PAGE_OFFS	(JAZZ_DMA_PAGE_SIZE-1)	/* page offset */
55#define JAZZ_DMA_PAGE_NUM	(~JAZZ_DMA_PAGE_OFFS)	/* page number */
56
57#define jazz_dma_page_offs(x)	\
58	((int)(x) & JAZZ_DMA_PAGE_OFFS)
59#define jazz_dma_page_round(x)	\
60	(((int)(x) + JAZZ_DMA_PAGE_OFFS) & JAZZ_DMA_PAGE_NUM)
61
62/*
63 *  DMA TLB entry
64 */
65
66typedef struct jazz_dma_pte {
67	uint32_t	lo_addr;	/* Low part of translation addr */
68	uint32_t	hi_addr;	/* High part of translation addr */
69} jazz_dma_pte_t;
70