1/* $NetBSD: sbicreg.h,v 1.9 2021/09/16 20:17:46 andvar Exp $ */ 2 3/* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsireg.h 7.3 (Berkeley) 2/5/91 35 */ 36 37/* 38 * AMD AM33C93A SCSI interface hardware description. 39 * 40 * Using parts of the Mach scsi driver for the 33C93 41 */ 42 43#define SBIC_myid 0 44#define SBIC_cdbsize 0 45#define SBIC_control 1 46#define SBIC_timeo 2 47#define SBIC_cdb1 3 48#define SBIC_tsecs 3 49#define SBIC_cdb2 4 50#define SBIC_theads 4 51#define SBIC_cdb3 5 52#define SBIC_tcyl_hi 5 53#define SBIC_cdb4 6 54#define SBIC_tcyl_lo 6 55#define SBIC_cdb5 7 56#define SBIC_addr_hi 7 57#define SBIC_cdb6 8 58#define SBIC_addr_2 8 59#define SBIC_cdb7 9 60#define SBIC_addr_3 9 61#define SBIC_cdb8 10 62#define SBIC_addr_lo 10 63#define SBIC_cdb9 11 64#define SBIC_secno 11 65#define SBIC_cdb10 12 66#define SBIC_headno 12 67#define SBIC_cdb11 13 68#define SBIC_cylno_hi 13 69#define SBIC_cdb12 14 70#define SBIC_cylno_lo 14 71#define SBIC_tlun 15 72#define SBIC_cmd_phase 16 73#define SBIC_syn 17 74#define SBIC_count_hi 18 75#define SBIC_count_med 19 76#define SBIC_count_lo 20 77#define SBIC_selid 21 78#define SBIC_rselid 22 79#define SBIC_csr 23 80#define SBIC_cmd 24 81#define SBIC_data 25 82/* sbic_asr is addressed directly */ 83 84/* 85 * Register defines 86 */ 87 88/* 89 * Auxiliary Status Register 90 */ 91 92#define SBIC_ASR_INT 0x80 /* Interrupt pending */ 93#define SBIC_ASR_LCI 0x40 /* Last command ignored */ 94#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */ 95#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */ 96#define SBIC_ASR_xxx 0x0c 97#define SBIC_ASR_PE 0x02 /* Parity error (even) */ 98#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */ 99 100/* 101 * My ID register, and/or CDB Size 102 */ 103 104#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 MHz */ 105 /* 11 MHz is invalid */ 106#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 MHz */ 107#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 MHz */ 108#define SBIC_ID_EHP 0x10 /* Enable host parity */ 109#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */ 110#define SBIC_ID_MASK 0x07 111#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */ 112 113/* 114 * Control register 115 */ 116 117#define SBIC_CTL_DMA 0x80 /* Single byte dma */ 118#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer access (bus master)*/ 119#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */ 120#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */ 121#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */ 122#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */ 123#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/ 124#define SBIC_CTL_HA 0x02 /* Halt on ATN */ 125#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */ 126 127/* 128 * Timeout period register 129 * [val in msecs, input clk in 0.1 MHz] 130 */ 131 132#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1) 133 134/* 135 * CDBn registers, note that 136 * cdb11 is used for status byte in target mode (send-status-and-cc) 137 * cdb12 sez if linked command complete, and w/flag if so 138 */ 139 140/* 141 * Target LUN register 142 * [holds target status when select-and-xfer] 143 */ 144 145#define SBIC_TLUN_VALID 0x80 /* did we receive an Identify msg */ 146#define SBIC_TLUN_DOK 0x40 /* Disconnect OK */ 147#define SBIC_TLUN_xxx 0x38 148#define SBIC_TLUN_MASK 0x07 149 150/* 151 * Command Phase register 152 */ 153 154#define SBIC_CPH_MASK 0x7f /* values/restarts are cmd specific */ 155#define SBIC_CPH(p) ((p) & SBIC_CPH_MASK) 156 157/* 158 * FIFO register 159 */ 160 161#define SBIC_FIFO_DEEP 12 162 163/* 164 * maximum possible size in TC registers. Since this is 24 bit, it's easy 165 */ 166#define SBIC_TC_MAX ((1 << 24) - 1) 167 168/* 169 * Synchronous xfer register 170 */ 171 172#define SBIC_SYN_OFF_MASK 0x0f 173#define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP 174#define SBIC_SYN_PER_MASK 0x70 175#define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */ 176 177#define SBIC_SYN(o,p) \ 178 (((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK)) 179 180/* 181 * Transfer count register 182 * optimal access macros depend on addressing 183 */ 184 185/* 186 * Destination ID (selid) register 187 */ 188 189#define SBIC_SID_SCC 0x80 /* Select command chaining (tgt) */ 190#define SBIC_SID_DPD 0x40 /* Data phase direction (inittor) */ 191#define SBIC_SID_FROM_SCSI 0x40 192#define SBIC_SID_TO_SCSI 0x00 193#define SBIC_SID_xxx 0x38 194#define SBIC_SID_IDMASK 0x07 195 196/* 197 * Source ID (rselid) register 198 */ 199 200#define SBIC_RID_ER 0x80 /* Enable reselection */ 201#define SBIC_RID_ES 0x40 /* Enable selection */ 202#define SBIC_RID_DSP 0x20 /* Disable select parity */ 203#define SBIC_RID_SIV 0x08 /* Source ID valid */ 204#define SBIC_RID_MASK 0x07 205 206/* 207 * Status register 208 */ 209 210#define SBIC_CSR_CAUSE 0xf0 211#define SBIC_CSR_RESET 0x00 /* chip was reset */ 212#define SBIC_CSR_CMD_DONE 0x10 /* cmd completed */ 213#define SBIC_CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/ 214#define SBIC_CSR_CMD_ERR 0x40 /* end with error */ 215#define SBIC_CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */ 216 217 218#define SBIC_CSR_QUALIFIER 0x0f 219/* Reset State Interrupts */ 220#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/ 221#define SBIC_CSR_RESET_AM 0x01 /* reset w/advanced features*/ 222/* Successful Completion Interrupts */ 223#define SBIC_CSR_TARGET 0x10 /* reselect complete */ 224#define SBIC_CSR_INITIATOR 0x11 /* select complete */ 225#define SBIC_CSR_WO_ATN 0x13 /* tgt mode completion */ 226#define SBIC_CSR_W_ATN 0x14 /* ditto */ 227#define SBIC_CSR_XLATED 0x15 /* translate address cmd */ 228#define SBIC_CSR_S_XFERRED 0x16 /* initiator mode completion*/ 229#define SBIC_CSR_XFERRED 0x18 /* phase in low bits */ 230/* Paused or Aborted Interrupts */ 231#define SBIC_CSR_MSGIN_W_ACK 0x20 /* (I) msgin, ACK asserted*/ 232#define SBIC_CSR_SDP 0x21 /* (I) SDP msg received */ 233#define SBIC_CSR_SEL_ABRT 0x22 /* sel/resel aborted */ 234#define SBIC_CSR_XFR_PAUSED 0x23 /* (T) no ATN */ 235#define SBIC_CSR_XFR_PAUSED_ATN 0x24 /* (T) ATN is asserted */ 236#define SBIC_CSR_RSLT_AM 0x27 /* (I) lost selection (AM) */ 237#define SBIC_CSR_MIS 0x28 /* (I) xfer aborted, ph mis */ 238/* Terminated Interrupts */ 239#define SBIC_CSR_CMD_INVALID 0x40 240#define SBIC_CSR_DISC 0x41 /* (I) tgt disconnected */ 241#define SBIC_CSR_SEL_TIMEO 0x42 242#define SBIC_CSR_PE 0x43 /* parity error */ 243#define SBIC_CSR_PE_ATN 0x44 /* ditto, ATN is asserted */ 244#define SBIC_CSR_XLATE_TOOBIG 0x45 245#define SBIC_CSR_RSLT_NOAM 0x46 /* (I) lost sel, no AM mode */ 246#define SBIC_CSR_BAD_STATUS 0x47 /* status byte was nok */ 247#define SBIC_CSR_MIS_1 0x48 /* ph mis, see low bits */ 248/* Service Required Interrupts */ 249#define SBIC_CSR_RSLT_NI 0x80 /* reselected, no ify msg */ 250#define SBIC_CSR_RSLT_IFY 0x81 /* ditto, AM mode, got ify */ 251#define SBIC_CSR_SLT 0x82 /* selected, no ATN */ 252#define SBIC_CSR_SLT_ATN 0x83 /* selected with ATN */ 253#define SBIC_CSR_ATN 0x84 /* (T) ATN asserted */ 254#define SBIC_CSR_DISC_1 0x85 /* (I) bus is free */ 255#define SBIC_CSR_UNK_GROUP 0x87 /* strange CDB1 */ 256#define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */ 257 258#define SBIC_PHASE(csr) SCSI_PHASE(csr) 259 260/* 261 * Command register (command codes) 262 */ 263 264#define SBIC_CMD_SBT 0x80 /* Single byte xfer qualifier */ 265#define SBIC_CMD_MASK 0x7f 266 267 /* Miscellaneous */ 268#define SBIC_CMD_RESET 0x00 /* (DTI) lev I */ 269#define SBIC_CMD_ABORT 0x01 /* (DTI) lev I */ 270#define SBIC_CMD_DISC 0x04 /* ( TI) lev I */ 271#define SBIC_CMD_SSCC 0x0d /* ( TI) lev I */ 272#define SBIC_CMD_SET_IDI 0x0f /* (DTI) lev I */ 273#define SBIC_CMD_XLATE 0x18 /* (DT ) lev II */ 274 275 /* Initiator state */ 276#define SBIC_CMD_SET_ATN 0x02 /* ( I) lev I */ 277#define SBIC_CMD_CLR_ACK 0x03 /* ( I) lev I */ 278#define SBIC_CMD_XFER_PAD 0x19 /* ( I) lev II */ 279#define SBIC_CMD_XFER_INFO 0x20 /* ( I) lev II */ 280 281 /* Target state */ 282#define SBIC_CMD_SND_DISC 0x0e /* ( T ) lev II */ 283#define SBIC_CMD_RCV_CMD 0x10 /* ( T ) lev II */ 284#define SBIC_CMD_RCV_DATA 0x11 /* ( T ) lev II */ 285#define SBIC_CMD_RCV_MSG_OUT 0x12 /* ( T ) lev II */ 286#define SBIC_CMD_RCV 0x13 /* ( T ) lev II */ 287#define SBIC_CMD_SND_STATUS 0x14 /* ( T ) lev II */ 288#define SBIC_CMD_SND_DATA 0x15 /* ( T ) lev II */ 289#define SBIC_CMD_SND_MSG_IN 0x16 /* ( T ) lev II */ 290#define SBIC_CMD_SND 0x17 /* ( T ) lev II */ 291 292 /* Disconnected state */ 293#define SBIC_CMD_RESELECT 0x05 /* (D ) lev II */ 294#define SBIC_CMD_SEL_ATN 0x06 /* (D ) lev II */ 295#define SBIC_CMD_SEL 0x07 /* (D ) lev II */ 296#define SBIC_CMD_SEL_ATN_XFER 0x08 /* (D I) lev II */ 297#define SBIC_CMD_SEL_XFER 0x09 /* (D I) lev II */ 298#define SBIC_CMD_RESELECT_RECV 0x0a /* (DT ) lev II */ 299#define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */ 300#define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */ 301 302/* approximate, but we won't do SBT on selects */ 303#define sbic_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa)) 304 305#define PAD(n) char n; 306#define SBIC_MACHINE_DMA_MODE SBIC_CTL_DMA 307 308typedef struct { 309 volatile unsigned char *sbic_asr_p; /* r : Aux Status Register */ 310#define sbic_address_p sbic_asr_p /* w : desired register no */ 311 volatile unsigned char *sbic_value_p; /* rw: register value */ 312} sbic_regmap_t; 313typedef sbic_regmap_t *sbic_regmap_p; 314 315#define sbic_read_reg(regs,regno,val) do { \ 316 *((regs).sbic_address_p) = (regno); \ 317 amiga_membarrier(); \ 318 (val) = *((regs).sbic_value_p); \ 319 amiga_membarrier(); \ 320 } while (0) 321 322#define sbic_write_reg(regs,regno,val) do { \ 323 *((regs).sbic_address_p) = (regno); \ 324 amiga_membarrier(); \ 325 *((regs).sbic_value_p) = (val); \ 326 amiga_membarrier(); \ 327 } while (0) 328 329#define SET_SBIC_myid(regs,val) sbic_write_reg(regs,SBIC_myid,val) 330#define GET_SBIC_myid(regs,val) sbic_read_reg(regs,SBIC_myid,val) 331#define SET_SBIC_cdbsize(regs,val) sbic_write_reg(regs,SBIC_cdbsize,val) 332#define GET_SBIC_cdbsize(regs,val) sbic_read_reg(regs,SBIC_cdbsize,val) 333#define SET_SBIC_control(regs,val) sbic_write_reg(regs,SBIC_control,val) 334#define GET_SBIC_control(regs,val) sbic_read_reg(regs,SBIC_control,val) 335#define SET_SBIC_timeo(regs,val) sbic_write_reg(regs,SBIC_timeo,val) 336#define GET_SBIC_timeo(regs,val) sbic_read_reg(regs,SBIC_timeo,val) 337#define SET_SBIC_cdb1(regs,val) sbic_write_reg(regs,SBIC_cdb1,val) 338#define GET_SBIC_cdb1(regs,val) sbic_read_reg(regs,SBIC_cdb1,val) 339#define SET_SBIC_cdb2(regs,val) sbic_write_reg(regs,SBIC_cdb2,val) 340#define GET_SBIC_cdb2(regs,val) sbic_read_reg(regs,SBIC_cdb2,val) 341#define SET_SBIC_cdb3(regs,val) sbic_write_reg(regs,SBIC_cdb3,val) 342#define GET_SBIC_cdb3(regs,val) sbic_read_reg(regs,SBIC_cdb3,val) 343#define SET_SBIC_cdb4(regs,val) sbic_write_reg(regs,SBIC_cdb4,val) 344#define GET_SBIC_cdb4(regs,val) sbic_read_reg(regs,SBIC_cdb4,val) 345#define SET_SBIC_cdb5(regs,val) sbic_write_reg(regs,SBIC_cdb5,val) 346#define GET_SBIC_cdb5(regs,val) sbic_read_reg(regs,SBIC_cdb5,val) 347#define SET_SBIC_cdb6(regs,val) sbic_write_reg(regs,SBIC_cdb6,val) 348#define GET_SBIC_cdb6(regs,val) sbic_read_reg(regs,SBIC_cdb6,val) 349#define SET_SBIC_cdb7(regs,val) sbic_write_reg(regs,SBIC_cdb7,val) 350#define GET_SBIC_cdb7(regs,val) sbic_read_reg(regs,SBIC_cdb7,val) 351#define SET_SBIC_cdb8(regs,val) sbic_write_reg(regs,SBIC_cdb8,val) 352#define GET_SBIC_cdb8(regs,val) sbic_read_reg(regs,SBIC_cdb8,val) 353#define SET_SBIC_cdb9(regs,val) sbic_write_reg(regs,SBIC_cdb9,val) 354#define GET_SBIC_cdb9(regs,val) sbic_read_reg(regs,SBIC_cdb9,val) 355#define SET_SBIC_cdb10(regs,val) sbic_write_reg(regs,SBIC_cdb10,val) 356#define GET_SBIC_cdb10(regs,val) sbic_read_reg(regs,SBIC_cdb10,val) 357#define SET_SBIC_cdb11(regs,val) sbic_write_reg(regs,SBIC_cdb11,val) 358#define GET_SBIC_cdb11(regs,val) sbic_read_reg(regs,SBIC_cdb11,val) 359#define SET_SBIC_cdb12(regs,val) sbic_write_reg(regs,SBIC_cdb12,val) 360#define GET_SBIC_cdb12(regs,val) sbic_read_reg(regs,SBIC_cdb12,val) 361#define SET_SBIC_tlun(regs,val) sbic_write_reg(regs,SBIC_tlun,val) 362#define GET_SBIC_tlun(regs,val) sbic_read_reg(regs,SBIC_tlun,val) 363#define SET_SBIC_cmd_phase(regs,val) sbic_write_reg(regs,SBIC_cmd_phase,val) 364#define GET_SBIC_cmd_phase(regs,val) sbic_read_reg(regs,SBIC_cmd_phase,val) 365#define SET_SBIC_syn(regs,val) sbic_write_reg(regs,SBIC_syn,val) 366#define GET_SBIC_syn(regs,val) sbic_read_reg(regs,SBIC_syn,val) 367#define SET_SBIC_count_hi(regs,val) sbic_write_reg(regs,SBIC_count_hi,val) 368#define GET_SBIC_count_hi(regs,val) sbic_read_reg(regs,SBIC_count_hi,val) 369#define SET_SBIC_count_med(regs,val) sbic_write_reg(regs,SBIC_count_med,val) 370#define GET_SBIC_count_med(regs,val) sbic_read_reg(regs,SBIC_count_med,val) 371#define SET_SBIC_count_lo(regs,val) sbic_write_reg(regs,SBIC_count_lo,val) 372#define GET_SBIC_count_lo(regs,val) sbic_read_reg(regs,SBIC_count_lo,val) 373#define SET_SBIC_selid(regs,val) sbic_write_reg(regs,SBIC_selid,val) 374#define GET_SBIC_selid(regs,val) sbic_read_reg(regs,SBIC_selid,val) 375#define SET_SBIC_rselid(regs,val) sbic_write_reg(regs,SBIC_rselid,val) 376#define GET_SBIC_rselid(regs,val) sbic_read_reg(regs,SBIC_rselid,val) 377#define SET_SBIC_csr(regs,val) sbic_write_reg(regs,SBIC_csr,val) 378#define GET_SBIC_csr(regs,val) sbic_read_reg(regs,SBIC_csr,val) 379#define SET_SBIC_cmd(regs,val) sbic_write_reg(regs,SBIC_cmd,val) 380#define GET_SBIC_cmd(regs,val) sbic_read_reg(regs,SBIC_cmd,val) 381#define SET_SBIC_data(regs,val) sbic_write_reg(regs,SBIC_data,val) 382#define GET_SBIC_data(regs,val) sbic_read_reg(regs,SBIC_data,val) 383 384#define SBIC_TC_PUT(regs,val) do { \ 385 sbic_write_reg(regs,SBIC_count_hi,((val)>>16)); \ 386 *((regs).sbic_value_p) = (val)>>8; \ 387 *((regs).sbic_value_p) = (val); \ 388} while (0) 389#define SBIC_TC_GET(regs,val) do { \ 390 sbic_read_reg(regs,SBIC_count_hi,(val)); \ 391 (val) = ((val)<<8) | *((regs).sbic_value_p); \ 392 (val) = ((val)<<8) | *((regs).sbic_value_p); \ 393} while (0) 394 395#define SBIC_LOAD_COMMAND(regs,cmd,cmdsize) do { \ 396 int n=(cmdsize)-1; \ 397 char *ptr = (char*)(cmd); \ 398 sbic_write_reg(regs,SBIC_cdb1,*ptr++); \ 399 while (n-- > 0) *((regs).sbic_value_p) = *ptr++; \ 400} while (0) 401 402#define GET_SBIC_asr(regs,val) (val) = *((regs).sbic_asr_p) 403 404#define WAIT_CIP(regs) do { \ 405 while (*((regs).sbic_asr_p) & SBIC_ASR_CIP) \ 406 ; \ 407} while (0) 408 409/* transmit a byte in programmed I/O mode */ 410#define SEND_BYTE(regs, ch) do { \ 411 WAIT_CIP(regs); \ 412 SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ 413 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \ 414 SET_SBIC_data(regs, ch); \ 415 } while (0) 416 417/* receive a byte in programmed I/O mode */ 418#define RECV_BYTE(regs, ch) do { \ 419 WAIT_CIP(regs); \ 420 SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \ 421 SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \ 422 GET_SBIC_data(regs, ch); \ 423 } while (0) 424