1258945Sroberto/* $NetBSD: grf_cvreg.h,v 1.19 2012/02/12 16:34:07 matt Exp $ */ 2280849Scy 3258945Sroberto/* 4258945Sroberto * Copyright (c) 1995 Michael Teske 5258945Sroberto * All rights reserved. 6258945Sroberto * 7258945Sroberto * Redistribution and use in source and binary forms, with or without 8258945Sroberto * modification, are permitted provided that the following conditions 9258945Sroberto * are met: 10258945Sroberto * 1. Redistributions of source code must retain the above copyright 11258945Sroberto * notice, this list of conditions and the following disclaimer. 12258945Sroberto * 2. Redistributions in binary form must reproduce the above copyright 13258945Sroberto * notice, this list of conditions and the following disclaimer in the 14258945Sroberto * documentation and/or other materials provided with the distribution. 15258945Sroberto * 3. All advertising materials mentioning features or use of this software 16258945Sroberto * must display the following acknowledgement: 17258945Sroberto * This product includes software developed by Ezra Story, by Kari 18280849Scy * Mettinen and by Bernd Ernesti. 19258945Sroberto * 4. The name of the author may not be used to endorse or promote products 20258945Sroberto * derived from this software without specific prior written permission 21258945Sroberto * 22258945Sroberto * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23258945Sroberto * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24258945Sroberto * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25258945Sroberto * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26258945Sroberto * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27258945Sroberto * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28258945Sroberto * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29258945Sroberto * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30258945Sroberto * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31258945Sroberto * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32258945Sroberto */ 33258945Sroberto 34258945Sroberto#ifndef _GRF_CVREG_H 35258945Sroberto#define _GRF_CVREG_H 36258945Sroberto 37258945Sroberto#include <machine/cpu.h> 38258945Sroberto 39258945Sroberto/* 40258945Sroberto * This is derived from Cirrus driver source 41258945Sroberto */ 42258945Sroberto 43258945Sroberto/* Extension to grfvideo_mode to support text modes. 44258945Sroberto * This can be passed to both text & gfx functions 45258945Sroberto * without worry. If gv.depth == 4, then the extended 46258945Sroberto * fields for a text mode are present. 47258945Sroberto */ 48258945Sroberto 49258945Srobertostruct grfcvtext_mode { 50258945Sroberto struct grfvideo_mode gv; 51258945Sroberto unsigned short fx; /* font x dimension */ 52258945Sroberto unsigned short fy; /* font y dimension */ 53258945Sroberto unsigned short cols; /* screen dimensions */ 54258945Sroberto unsigned short rows; 55258945Sroberto void *fdata; /* font data */ 56258945Sroberto unsigned short fdstart; 57258945Sroberto unsigned short fdend; 58258945Sroberto}; 59258945Sroberto 60258945Sroberto 61258945Sroberto/* read VGA register */ 62258945Sroberto#define vgar(ba, reg) \ 63258945Sroberto (*(((volatile char *)ba)+reg)) 64258945Sroberto 65258945Sroberto/* write VGA register */ 66258945Sroberto#define vgaw(ba, reg, val) \ 67258945Sroberto *(((volatile char *)ba)+reg) = ((val) & 0xff); \ 68258945Sroberto amiga_membarrier() 69258945Sroberto 70258945Sroberto/* read 32 Bit VGA register */ 71258945Sroberto#define vgar32(ba, reg) \ 72258945Sroberto ( *((volatile unsigned long *) (((volatile char *)ba)+reg)) ) 73258945Sroberto 74258945Sroberto/* write 32 Bit VGA register */ 75258945Sroberto#define vgaw32(ba, reg, val) \ 76258945Sroberto *((unsigned long *) (((volatile char *)ba)+reg)) = val; \ 77258945Sroberto amiga_membarrier() 78258945Sroberto 79258945Sroberto/* read 16 Bit VGA register */ 80258945Sroberto#define vgar16(ba, reg) \ 81258945Sroberto ( *((volatile unsigned short *) (((volatile char *)ba)+reg)) ) 82258945Sroberto 83258945Sroberto/* write 16 Bit VGA register */ 84258945Sroberto#define vgaw16(ba, reg, val) \ 85258945Sroberto *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val; \ 86258945Sroberto amiga_membarrier() 87258945Sroberto 88258945Sroberto#ifdef _KERNEL 89258945Srobertoint grfcv_cnprobe(void); 90258945Srobertovoid grfcv_iteinit(struct grf_softc *); 91258945Srobertostatic inline void GfxBusyWait(volatile void *); 92258945Srobertostatic inline void GfxFifoWait(volatile void *); 93258945Srobertostatic inline unsigned char RAttr(volatile void *, short); 94258945Srobertostatic inline unsigned char RSeq(volatile void *, short); 95258945Srobertostatic inline unsigned char RCrt(volatile void *, short); 96258945Srobertostatic inline unsigned char RGfx(volatile void *, short); 97258945Sroberto#endif 98258945Sroberto 99258945Sroberto 100258945Sroberto/* 101258945Sroberto * defines for the used register addresses (mw) 102258945Sroberto * 103258945Sroberto * NOTE: there are some registers that have different addresses when 104258945Sroberto * in mono or color mode. We only support color mode, and thus 105258945Sroberto * some addresses won't work in mono-mode! 106258945Sroberto * 107258945Sroberto * General and VGA-registers taken from retina driver. Fixed a few 108258945Sroberto * bugs in it. (SR and GR read address is Port + 1, NOT Port) 109258945Sroberto * 110258945Sroberto */ 111258945Sroberto 112258945Sroberto/* General Registers: */ 113258945Sroberto#define GREG_MISC_OUTPUT_R 0x03CC 114258945Sroberto#define GREG_MISC_OUTPUT_W 0x03C2 115258945Sroberto#define GREG_FEATURE_CONTROL_R 0x03CA 116258945Sroberto#define GREG_FEATURE_CONTROL_W 0x03DA 117258945Sroberto#define GREG_INPUT_STATUS0_R 0x03C2 118258945Sroberto#define GREG_INPUT_STATUS1_R 0x03DA 119258945Sroberto 120258945Sroberto/* Setup Registers: */ 121258945Sroberto#define SREG_OPTION_SELECT 0x0102 122258945Sroberto#define SREG_VIDEO_SUBS_ENABLE 0x46E8 123258945Sroberto 124258945Sroberto/* Attribute Controller: */ 125258945Sroberto#define ACT_ADDRESS 0x03C0 126258945Sroberto#define ACT_ADDRESS_R 0x03C1 127258945Sroberto#define ACT_ADDRESS_W 0x03C0 128258945Sroberto#define ACT_ADDRESS_RESET 0x03DA 129258945Sroberto#define ACT_ID_PALETTE0 0x00 130258945Sroberto#define ACT_ID_PALETTE1 0x01 131258945Sroberto#define ACT_ID_PALETTE2 0x02 132258945Sroberto#define ACT_ID_PALETTE3 0x03 133258945Sroberto#define ACT_ID_PALETTE4 0x04 134258945Sroberto#define ACT_ID_PALETTE5 0x05 135258945Sroberto#define ACT_ID_PALETTE6 0x06 136258945Sroberto#define ACT_ID_PALETTE7 0x07 137293893Sglebius#define ACT_ID_PALETTE8 0x08 138258945Sroberto#define ACT_ID_PALETTE9 0x09 139258945Sroberto#define ACT_ID_PALETTE10 0x0A 140258945Sroberto#define ACT_ID_PALETTE11 0x0B 141258945Sroberto#define ACT_ID_PALETTE12 0x0C 142258945Sroberto#define ACT_ID_PALETTE13 0x0D 143258945Sroberto#define ACT_ID_PALETTE14 0x0E 144258945Sroberto#define ACT_ID_PALETTE15 0x0F 145258945Sroberto#define ACT_ID_ATTR_MODE_CNTL 0x10 146258945Sroberto#define ACT_ID_OVERSCAN_COLOR 0x11 147258945Sroberto#define ACT_ID_COLOR_PLANE_ENA 0x12 148258945Sroberto#define ACT_ID_HOR_PEL_PANNING 0x13 149258945Sroberto#define ACT_ID_COLOR_SELECT 0x14 150258945Sroberto 151258945Sroberto/* Graphics Controller: */ 152258945Sroberto#define GCT_ADDRESS 0x03CE 153258945Sroberto#define GCT_ADDRESS_R 0x03CF 154258945Sroberto#define GCT_ADDRESS_W 0x03CF 155258945Sroberto#define GCT_ID_SET_RESET 0x00 156293893Sglebius#define GCT_ID_ENABLE_SET_RESET 0x01 157258945Sroberto#define GCT_ID_COLOR_COMPARE 0x02 158258945Sroberto#define GCT_ID_DATA_ROTATE 0x03 159258945Sroberto#define GCT_ID_READ_MAP_SELECT 0x04 160258945Sroberto#define GCT_ID_GRAPHICS_MODE 0x05 161258945Sroberto#define GCT_ID_MISC 0x06 162258945Sroberto#define GCT_ID_COLOR_XCARE 0x07 163258945Sroberto#define GCT_ID_BITMASK 0x08 164258945Sroberto 165258945Sroberto/* Sequencer: */ 166258945Sroberto#define SEQ_ADDRESS 0x03C4 167258945Sroberto#define SEQ_ADDRESS_R 0x03C5 168258945Sroberto#define SEQ_ADDRESS_W 0x03C5 169258945Sroberto#define SEQ_ID_RESET 0x00 170258945Sroberto#define SEQ_ID_CLOCKING_MODE 0x01 171258945Sroberto#define SEQ_ID_MAP_MASK 0x02 172258945Sroberto#define SEQ_ID_CHAR_MAP_SELECT 0x03 173258945Sroberto#define SEQ_ID_MEMORY_MODE 0x04 174258945Sroberto#define SEQ_ID_UNKNOWN1 0x05 175258945Sroberto#define SEQ_ID_UNKNOWN2 0x06 176258945Sroberto#define SEQ_ID_UNKNOWN3 0x07 177258945Sroberto/* S3 extensions */ 178258945Sroberto#define SEQ_ID_UNLOCK_EXT 0x08 179258945Sroberto#define SEQ_ID_EXT_SEQ_REG9 0x09 180258945Sroberto#define SEQ_ID_BUS_REQ_CNTL 0x0A 181258945Sroberto#define SEQ_ID_EXT_MISC_SEQ 0x0B 182258945Sroberto#define SEQ_ID_UNKNOWN4 0x0C 183258945Sroberto#define SEQ_ID_EXT_SEQ 0x0D 184258945Sroberto#define SEQ_ID_UNKNOWN5 0x0E 185280849Scy#define SEQ_ID_UNKNOWN6 0x0F 186280849Scy#define SEQ_ID_MCLK_LO 0x10 187280849Scy#define SEQ_ID_MCLK_HI 0x11 188258945Sroberto#define SEQ_ID_DCLK_LO 0x12 189258945Sroberto#define SEQ_ID_DCLK_HI 0x13 190258945Sroberto#define SEQ_ID_CLKSYN_CNTL_1 0x14 191258945Sroberto#define SEQ_ID_CLKSYN_CNTL_2 0x15 192258945Sroberto#define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 193258945Sroberto#define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 194258945Sroberto#define SEQ_ID_RAMDAC_CNTL 0x18 195280849Scy#define SEQ_ID_MORE_MAGIC 0x1A 196258945Sroberto 197258945Sroberto/* CRT Controller: */ 198280849Scy#define CRT_ADDRESS 0x03D4 199258945Sroberto#define CRT_ADDRESS_R 0x03D5 200258945Sroberto#define CRT_ADDRESS_W 0x03D5 201258945Sroberto#define CRT_ID_HOR_TOTAL 0x00 202258945Sroberto#define CRT_ID_HOR_DISP_ENA_END 0x01 203258945Sroberto#define CRT_ID_START_HOR_BLANK 0x02 204258945Sroberto#define CRT_ID_END_HOR_BLANK 0x03 205258945Sroberto#define CRT_ID_START_HOR_RETR 0x04 206258945Sroberto#define CRT_ID_END_HOR_RETR 0x05 207258945Sroberto#define CRT_ID_VER_TOTAL 0x06 208258945Sroberto#define CRT_ID_OVERFLOW 0x07 209258945Sroberto#define CRT_ID_PRESET_ROW_SCAN 0x08 210258945Sroberto#define CRT_ID_MAX_SCAN_LINE 0x09 211258945Sroberto#define CRT_ID_CURSOR_START 0x0A 212258945Sroberto#define CRT_ID_CURSOR_END 0x0B 213258945Sroberto#define CRT_ID_START_ADDR_HIGH 0x0C 214258945Sroberto#define CRT_ID_START_ADDR_LOW 0x0D 215258945Sroberto#define CRT_ID_CURSOR_LOC_HIGH 0x0E 216258945Sroberto#define CRT_ID_CURSOR_LOC_LOW 0x0F 217258945Sroberto#define CRT_ID_START_VER_RETR 0x10 218258945Sroberto#define CRT_ID_END_VER_RETR 0x11 219258945Sroberto#define CRT_ID_VER_DISP_ENA_END 0x12 220258945Sroberto#define CRT_ID_SCREEN_OFFSET 0x13 221258945Sroberto#define CRT_ID_UNDERLINE_LOC 0x14 222258945Sroberto#define CRT_ID_START_VER_BLANK 0x15 223258945Sroberto#define CRT_ID_END_VER_BLANK 0x16 224280849Scy#define CRT_ID_MODE_CONTROL 0x17 225258945Sroberto#define CRT_ID_LINE_COMPARE 0x18 226258945Sroberto#define CRT_ID_GD_LATCH_RBACK 0x22 227258945Sroberto#define CRT_ID_ACT_TOGGLE_RBACK 0x24 228258945Sroberto#define CRT_ID_ACT_INDEX_RBACK 0x26 229258945Sroberto/* S3 extensions: S3 VGA Registers */ 230258945Sroberto#define CRT_ID_DEVICE_HIGH 0x2D 231258945Sroberto#define CRT_ID_DEVICE_LOW 0x2E 232258945Sroberto#define CRT_ID_REVISION 0x2F 233258945Sroberto#define CRT_ID_CHIP_ID_REV 0x30 234280849Scy#define CRT_ID_MEMORY_CONF 0x31 235258945Sroberto#define CRT_ID_BACKWAD_COMP_1 0x32 236258945Sroberto#define CRT_ID_BACKWAD_COMP_2 0x33 237258945Sroberto#define CRT_ID_BACKWAD_COMP_3 0x34 238280849Scy#define CRT_ID_REGISTER_LOCK 0x35 239258945Sroberto#define CRT_ID_CONFIG_1 0x36 240258945Sroberto#define CRT_ID_CONFIG_2 0x37 241258945Sroberto#define CRT_ID_REGISTER_LOCK_1 0x38 242258945Sroberto#define CRT_ID_REGISTER_LOCK_2 0x39 243258945Sroberto#define CRT_ID_MISC_1 0x3A 244258945Sroberto#define CRT_ID_DISPLAY_FIFO 0x3B 245258945Sroberto#define CRT_ID_LACE_RETR_START 0x3C 246258945Sroberto/* S3 extensions: System Control Registers */ 247258945Sroberto#define CRT_ID_SYSTEM_CONFIG 0x40 248258945Sroberto#define CRT_ID_BIOS_FLAG 0x41 249258945Sroberto#define CRT_ID_LACE_CONTROL 0x42 250258945Sroberto#define CRT_ID_EXT_MODE 0x43 251258945Sroberto#define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 252258945Sroberto#define CRT_ID_HWGC_ORIGIN_X_HI 0x46 253258945Sroberto#define CRT_ID_HWGC_ORIGIN_X_LO 0x47 254258945Sroberto#define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 255258945Sroberto#define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 256258945Sroberto#define CRT_ID_HWGC_FG_STACK 0x4A 257258945Sroberto#define CRT_ID_HWGC_BG_STACK 0x4B 258258945Sroberto#define CRT_ID_HWGC_START_AD_HI 0x4C 259258945Sroberto#define CRT_ID_HWGC_START_AD_LO 0x4D 260258945Sroberto#define CRT_ID_HWGC_DSTART_X 0x4E 261258945Sroberto#define CRT_ID_HWGC_DSTART_Y 0x4F 262258945Sroberto/* S3 extensions: System Extension Registers */ 263258945Sroberto#define CRT_ID_EXT_SYS_CNTL_1 0x50 264258945Sroberto#define CRT_ID_EXT_SYS_CNTL_2 0x51 265258945Sroberto#define CRT_ID_EXT_BIOS_FLAG_1 0x52 266258945Sroberto#define CRT_ID_EXT_MEM_CNTL_1 0x53 267258945Sroberto#define CRT_ID_EXT_MEM_CNTL_2 0x54 268258945Sroberto#define CRT_ID_EXT_DAC_CNTL 0x55 269258945Sroberto#define CRT_ID_EX_SYNC_1 0x56 270258945Sroberto#define CRT_ID_EX_SYNC_2 0x57 271258945Sroberto#define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 272258945Sroberto#define CRT_ID_LAW_POS_HI 0x59 273258945Sroberto#define CRT_ID_LAW_POS_LO 0x5A 274258945Sroberto#define CRT_ID_GOUT_PORT 0x5C 275258945Sroberto#define CRT_ID_EXT_HOR_OVF 0x5D 276258945Sroberto#define CRT_ID_EXT_VER_OVF 0x5E 277258945Sroberto#define CRT_ID_EXT_MEM_CNTL_3 0x60 278258945Sroberto#define CRT_ID_EX_SYNC_3 0x63 279258945Sroberto#define CRT_ID_EXT_MISC_CNTL 0x65 280258945Sroberto#define CRT_ID_EXT_MISC_CNTL_1 0x66 281258945Sroberto#define CRT_ID_EXT_MISC_CNTL_2 0x67 282258945Sroberto#define CRT_ID_CONFIG_3 0x68 283258945Sroberto#define CRT_ID_EXT_SYS_CNTL_3 0x69 284258945Sroberto#define CRT_ID_EXT_SYS_CNTL_4 0x6A 285258945Sroberto#define CRT_ID_EXT_BIOS_FLAG_3 0x6B 286258945Sroberto#define CRT_ID_EXT_BIOS_FLAG_4 0x6C 287258945Sroberto 288258945Sroberto/* Enhanced Commands Registers: */ 289258945Sroberto#define ECR_SUBSYSTEM_STAT 0x42E8 290258945Sroberto#define ECR_SUBSYSTEM_CNTL 0x42E8 291258945Sroberto#define ECR_ADV_FUNC_CNTL 0x4AE8 292258945Sroberto#define ECR_CURRENT_Y_POS 0x82E8 293258945Sroberto#define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */ 294258945Sroberto#define ECR_CURRENT_X_POS 0x86E8 295258945Sroberto#define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */ 296258945Sroberto#define ECR_DEST_Y__AX_STEP 0x8AE8 297258945Sroberto#define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */ 298258945Sroberto#define ECR_DEST_X__DIA_STEP 0x8EE8 299258945Sroberto#define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */ 300258945Sroberto#define ECR_ERR_TERM 0x92E8 301258945Sroberto#define ECR_ERR_TERM2 0x92EA /* Trio64 only */ 302258945Sroberto#define ECR_MAJ_AXIS_PIX_CNT 0x96E8 303258945Sroberto#define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */ 304258945Sroberto#define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */ 305258945Sroberto#define ECR_DRAW_CMD 0x9AE8 306258945Sroberto#define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */ 307258945Sroberto#define ECR_SHORT_STROKE 0x9EE8 308258945Sroberto#define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */ 309258945Sroberto#define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */ 310258945Sroberto#define ECR_BITPLANE_WRITE_MASK 0xAAE8 311258945Sroberto#define ECR_BITPLANE_READ_MASK 0xAEE8 312258945Sroberto#define ECR_COLOR_COMPARE 0xB2E8 313258945Sroberto#define ECR_BKGD_MIX 0xB6E8 314258945Sroberto#define ECR_FRGD_MIX 0xBAE8 315258945Sroberto#define ECR_READ_REG_DATA 0xBEE8 316258945Sroberto#define ECR_ID_MIN_AXIS_PIX_CNT 0x00 317258945Sroberto#define ECR_ID_SCISSORS_TOP 0x01 318258945Sroberto#define ECR_ID_SCISSORS_LEFT 0x02 319258945Sroberto#define ECR_ID_SCISSORS_BUTTOM 0x03 320258945Sroberto#define ECR_ID_SCISSORS_RIGHT 0x04 321258945Sroberto#define ECR_ID_PIX_CNTL 0x0A 322258945Sroberto#define ECR_ID_MULT_CNTL_MISC_2 0x0D 323258945Sroberto#define ECR_ID_MULT_CNTL_MISC 0x0E 324258945Sroberto#define ECR_ID_READ_SEL 0x0F 325258945Sroberto#define ECR_PIX_TRANS 0xE2E8 326258945Sroberto#define ECR_PIX_TRANS_EXT 0xE2EA 327258945Sroberto#define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */ 328258945Sroberto#define ECR_PATTERN_X 0xEAEA /* Trio64 only */ 329258945Sroberto 330258945Sroberto 331258945Sroberto/* Pass-through */ 332258945Sroberto#define PASS_ADDRESS 0x40001 333258945Sroberto#define PASS_ADDRESS_W 0x40001 334258945Sroberto 335258945Sroberto/* Video DAC */ 336258945Sroberto#define VDAC_ADDRESS 0x03c8 337258945Sroberto#define VDAC_ADDRESS_W 0x03c8 338258945Sroberto#define VDAC_ADDRESS_R 0x03c7 339258945Sroberto#define VDAC_STATE 0x03c7 340258945Sroberto#define VDAC_DATA 0x03c9 341258945Sroberto#define VDAC_MASK 0x03c6 342258945Sroberto 343258945Sroberto 344258945Sroberto#define WGfx(ba, idx, val) \ 345258945Sroberto do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 346258945Sroberto 347258945Sroberto#define WSeq(ba, idx, val) \ 348258945Sroberto do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 349258945Sroberto 350258945Sroberto#define WCrt(ba, idx, val) \ 351258945Sroberto do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 352258945Sroberto 353258945Sroberto#define WAttr(ba, idx, val) \ 354258945Sroberto do { \ 355258945Sroberto unsigned char tmp;\ 356258945Sroberto tmp = vgar(ba, ACT_ADDRESS_RESET);\ 357258945Sroberto __USE(tmp);\ 358258945Sroberto vgaw(ba, ACT_ADDRESS_W, idx);\ 359258945Sroberto vgaw(ba, ACT_ADDRESS_W, val);\ 360258945Sroberto } while (0) 361258945Sroberto 362258945Sroberto 363258945Sroberto#define SetTextPlane(ba, m) \ 364258945Sroberto do { \ 365258945Sroberto WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 366258945Sroberto WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 367258945Sroberto } while (0) 368258945Sroberto 369258945Sroberto 370258945Sroberto/* Gfx engine busy wait */ 371258945Sroberto#ifdef _KERNEL 372258945Srobertostatic inline void 373258945SrobertoGfxBusyWait (volatile void *ba) 374258945Sroberto{ 375258945Sroberto int test; 376258945Sroberto 377258945Sroberto do { 378258945Sroberto test = vgar16 (ba, ECR_GP_STAT); 379258945Sroberto amiga_cpu_sync(); 380258945Sroberto } while (test & (1 << 9)); 381258945Sroberto} 382258945Sroberto 383258945Sroberto 384258945Srobertostatic inline void 385258945SrobertoGfxFifoWait(volatile void *ba) 386258945Sroberto{ 387258945Sroberto int test; 388258945Sroberto 389258945Sroberto do { 390258945Sroberto test = vgar16 (ba, ECR_GP_STAT); 391258945Sroberto } while (test & 0x0f); 392258945Sroberto} 393258945Sroberto 394258945Sroberto 395258945Sroberto/* Special wakeup/passthrough registers on graphics boards 396258945Sroberto * 397258945Sroberto * The methods have diverged a bit for each board, so 398280849Scy * WPass(P) has been converted into a set of specific 399280849Scy * inline functions. 400258945Sroberto */ 401258945Sroberto 402258945Srobertostatic inline unsigned char 403258945SrobertoRAttr(volatile void *ba, short idx) 404258945Sroberto{ 405258945Sroberto 406258945Sroberto vgaw(ba, ACT_ADDRESS_W, idx); 407258945Sroberto delay(0); 408258945Sroberto return vgar(ba, ACT_ADDRESS_R); 409258945Sroberto} 410258945Sroberto 411258945Srobertostatic inline unsigned char 412258945SrobertoRSeq(volatile void *ba, short idx) 413258945Sroberto{ 414258945Sroberto vgaw(ba, SEQ_ADDRESS, idx); 415280849Scy return vgar(ba, SEQ_ADDRESS_R); 416258945Sroberto} 417258945Sroberto 418280849Scystatic inline unsigned char 419258945SrobertoRCrt(volatile void *ba, short idx) 420258945Sroberto{ 421258945Sroberto vgaw(ba, CRT_ADDRESS, idx); 422258945Sroberto return vgar(ba, CRT_ADDRESS_R); 423258945Sroberto} 424258945Sroberto 425258945Srobertostatic inline unsigned char 426258945SrobertoRGfx(volatile void *ba, short idx) 427258945Sroberto{ 428258945Sroberto vgaw(ba, GCT_ADDRESS, idx); 429258945Sroberto return vgar(ba, GCT_ADDRESS_R); 430258945Sroberto} 431258945Sroberto#endif 432258945Sroberto 433258945Sroberto#endif /* _GRF_CVREG_H */ 434258945Sroberto