grf_cv3dreg.h revision 1.8
1/* $NetBSD: grf_cv3dreg.h,v 1.8 2007/03/04 05:59:19 christos Exp $ */ 2 3/* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story and by Kari 18 * Mettinen. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _GRF_CV3DREG_H 35#define _GRF_CV3DREG_H 36 37/* 38 * This is derived from ciruss driver source 39 */ 40 41/* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47struct grfcv3dtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56}; 57 58/* maximum console size */ 59#define MAXROWS 200 60#define MAXCOLS 200 61 62/* read VGA register */ 63#define vgar(ba, reg) (*((volatile void *)(((void *)ba)+(reg ^ 3)))) 64 65/* write VGA register */ 66#define vgaw(ba, reg, val) \ 67 *((volatile void *)(((void *)ba)+(reg ^ 3))) = ((val) & 0xff) 68 69/* MMIO access */ 70#define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) ) 71 72#define vgario(ba, reg) \ 73 (*((volatile void *)(((void *)ba) + ( ByteAccessIO(reg) )))) 74 75#define vgawio(ba, reg, val) \ 76 do { \ 77 if (!cv3d_zorroIII) { \ 78 *((volatile void *)(((void *)cv3d_vcode_switch_base) + \ 79 0x04)) = (0x01 & 0xffff); \ 80 __asm volatile ("nop"); \ 81 } \ 82 *((volatile void *)(((void *)cv3d_special_register_base) + \ 83 ( ByteAccessIO(reg) & 0xffff ))) = ((val) & 0xff); \ 84 if (!cv3d_zorroIII) { \ 85 *((volatile void *)(((void *)cv3d_vcode_switch_base) + \ 86 0x04)) = (0x02 & 0xffff); \ 87 __asm volatile ("nop"); \ 88 } \ 89 } while (0) 90 91/* read 32 Bit VGA register */ 92#define vgar32(ba, reg) ( *((unsigned long *) (((volatile void *)ba)+reg)) ) 93 94/* write 32 Bit VGA register */ 95#define vgaw32(ba, reg, val) \ 96 *((unsigned long *) (((volatile void *)ba)+reg)) = val 97 98/* read 16 Bit VGA register */ 99#define vgar16(ba, reg) ( *((unsigned short *) (((volatile void *)ba)+reg)) ) 100 101/* write 16 Bit VGA register */ 102#define vgaw16(ba, reg, val) \ 103 *((unsigned short *) (((volatile void *)ba)+reg)) = val 104 105/* XXX This is totaly untested */ 106#define Select_Zorro2_FrameBuffer(flag) \ 107 do { \ 108 *((volatile void *)(((void *)cv3d_vcode_switch_base) + \ 109 0x08)) = ((flag * 0x40) & 0xffff); \ 110 __asm volatile ("nop"); \ 111} while (0) 112 113int grfcv3d_cnprobe(void); 114void grfcv3d_iteinit(struct grf_softc *); 115static inline void GfxBusyWait(volatile void *); 116static inline void GfxFifoWait(volatile void *); 117static inline unsigned char RAttr(volatile void *, short); 118static inline unsigned char RSeq(volatile void *, short); 119static inline unsigned char RCrt(volatile void *, short); 120static inline unsigned char RGfx(volatile void *, short); 121 122 123/* 124 * defines for the used register addresses (mw) 125 * 126 * NOTE: there are some registers that have different addresses when 127 * in mono or color mode. We only support color mode, and thus 128 * some addresses won't work in mono-mode! 129 * 130 * General and VGA-registers taken from retina driver. Fixed a few 131 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 132 * 133 */ 134 135/* General Registers: */ 136#define GREG_MISC_OUTPUT_R 0x03CC 137#define GREG_MISC_OUTPUT_W 0x03C2 138#define GREG_FEATURE_CONTROL_R 0x03CA 139#define GREG_FEATURE_CONTROL_W 0x03DA 140#define GREG_INPUT_STATUS0_R 0x03C2 141#define GREG_INPUT_STATUS1_R 0x03DA 142 143/* Setup Registers: */ 144#define SREG_OPTION_SELECT 0x0102 145#define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */ 146 147/* Attribute Controller: */ 148#define ACT_ADDRESS 0x03C0 149#define ACT_ADDRESS_R 0x03C1 150#define ACT_ADDRESS_W 0x03C0 151#define ACT_ADDRESS_RESET 0x03DA 152#define ACT_ID_PALETTE0 0x00 153#define ACT_ID_PALETTE1 0x01 154#define ACT_ID_PALETTE2 0x02 155#define ACT_ID_PALETTE3 0x03 156#define ACT_ID_PALETTE4 0x04 157#define ACT_ID_PALETTE5 0x05 158#define ACT_ID_PALETTE6 0x06 159#define ACT_ID_PALETTE7 0x07 160#define ACT_ID_PALETTE8 0x08 161#define ACT_ID_PALETTE9 0x09 162#define ACT_ID_PALETTE10 0x0A 163#define ACT_ID_PALETTE11 0x0B 164#define ACT_ID_PALETTE12 0x0C 165#define ACT_ID_PALETTE13 0x0D 166#define ACT_ID_PALETTE14 0x0E 167#define ACT_ID_PALETTE15 0x0F 168#define ACT_ID_ATTR_MODE_CNTL 0x10 169#define ACT_ID_OVERSCAN_COLOR 0x11 170#define ACT_ID_COLOR_PLANE_ENA 0x12 171#define ACT_ID_HOR_PEL_PANNING 0x13 172#define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */ 173 174/* Graphics Controller: */ 175#define GCT_ADDRESS 0x03CE 176#define GCT_ADDRESS_R 0x03CF 177#define GCT_ADDRESS_W 0x03CF 178#define GCT_ID_SET_RESET 0x00 179#define GCT_ID_ENABLE_SET_RESET 0x01 180#define GCT_ID_COLOR_COMPARE 0x02 181#define GCT_ID_DATA_ROTATE 0x03 182#define GCT_ID_READ_MAP_SELECT 0x04 183#define GCT_ID_GRAPHICS_MODE 0x05 184#define GCT_ID_MISC 0x06 185#define GCT_ID_COLOR_XCARE 0x07 186#define GCT_ID_BITMASK 0x08 187 188/* Sequencer: */ 189#define SEQ_ADDRESS 0x03C4 190#define SEQ_ADDRESS_R 0x03C5 191#define SEQ_ADDRESS_W 0x03C5 192#define SEQ_ID_RESET 0x00 193#define SEQ_ID_CLOCKING_MODE 0x01 194#define SEQ_ID_MAP_MASK 0x02 195#define SEQ_ID_CHAR_MAP_SELECT 0x03 196#define SEQ_ID_MEMORY_MODE 0x04 197#define SEQ_ID_UNKNOWN1 0x05 198#define SEQ_ID_UNKNOWN2 0x06 199#define SEQ_ID_UNKNOWN3 0x07 200/* S3 extensions */ 201#define SEQ_ID_UNLOCK_EXT 0x08 202#define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */ 203#define SEQ_ID_BUS_REQ_CNTL 0x0A 204#define SEQ_ID_EXT_MISC_SEQ 0x0B 205#define SEQ_ID_UNKNOWN4 0x0C 206#define SEQ_ID_EXT_SEQ 0x0D 207#define SEQ_ID_UNKNOWN5 0x0E 208#define SEQ_ID_UNKNOWN6 0x0F 209#define SEQ_ID_MCLK_LO 0x10 210#define SEQ_ID_MCLK_HI 0x11 211#define SEQ_ID_DCLK_LO 0x12 212#define SEQ_ID_DCLK_HI 0x13 213#define SEQ_ID_CLKSYN_CNTL_1 0x14 214#define SEQ_ID_CLKSYN_CNTL_2 0x15 215#define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 216#define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 217#define SEQ_ID_RAMDAC_CNTL 0x18 218#define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */ 219#define SEQ_ID_SIGNAL_SELECT 0x1C 220 221/* CRT Controller: */ 222#define CRT_ADDRESS 0x03D4 223#define CRT_ADDRESS_R 0x03D5 224#define CRT_ADDRESS_W 0x03D5 225#define CRT_ID_HOR_TOTAL 0x00 226#define CRT_ID_HOR_DISP_ENA_END 0x01 227#define CRT_ID_START_HOR_BLANK 0x02 228#define CRT_ID_END_HOR_BLANK 0x03 229#define CRT_ID_START_HOR_RETR 0x04 230#define CRT_ID_END_HOR_RETR 0x05 231#define CRT_ID_VER_TOTAL 0x06 232#define CRT_ID_OVERFLOW 0x07 233#define CRT_ID_PRESET_ROW_SCAN 0x08 234#define CRT_ID_MAX_SCAN_LINE 0x09 235#define CRT_ID_CURSOR_START 0x0A 236#define CRT_ID_CURSOR_END 0x0B 237#define CRT_ID_START_ADDR_HIGH 0x0C 238#define CRT_ID_START_ADDR_LOW 0x0D 239#define CRT_ID_CURSOR_LOC_HIGH 0x0E 240#define CRT_ID_CURSOR_LOC_LOW 0x0F 241#define CRT_ID_START_VER_RETR 0x10 242#define CRT_ID_END_VER_RETR 0x11 243#define CRT_ID_VER_DISP_ENA_END 0x12 244#define CRT_ID_SCREEN_OFFSET 0x13 245#define CRT_ID_UNDERLINE_LOC 0x14 246#define CRT_ID_START_VER_BLANK 0x15 247#define CRT_ID_END_VER_BLANK 0x16 248#define CRT_ID_MODE_CONTROL 0x17 249#define CRT_ID_LINE_COMPARE 0x18 250#define CRT_ID_GD_LATCH_RBACK 0x22 251#define CRT_ID_ACT_TOGGLE_RBACK 0x24 252#define CRT_ID_ACT_INDEX_RBACK 0x26 253/* S3 extensions: S3 VGA Registers */ 254#define CRT_ID_DEVICE_HIGH 0x2D 255#define CRT_ID_DEVICE_LOW 0x2E 256#define CRT_ID_REVISION 0x2F 257#define CRT_ID_CHIP_ID_REV 0x30 258#define CRT_ID_MEMORY_CONF 0x31 259#define CRT_ID_BACKWAD_COMP_1 0x32 260#define CRT_ID_BACKWAD_COMP_2 0x33 261#define CRT_ID_BACKWAD_COMP_3 0x34 262#define CRT_ID_REGISTER_LOCK 0x35 263#define CRT_ID_CONFIG_1 0x36 264#define CRT_ID_CONFIG_2 0x37 265#define CRT_ID_REGISTER_LOCK_1 0x38 266#define CRT_ID_REGISTER_LOCK_2 0x39 267#define CRT_ID_MISC_1 0x3A 268#define CRT_ID_DISPLAY_FIFO 0x3B 269#define CRT_ID_LACE_RETR_START 0x3C 270/* S3 extensions: System Control Registers */ 271#define CRT_ID_SYSTEM_CONFIG 0x40 272#define CRT_ID_BIOS_FLAG 0x41 273#define CRT_ID_LACE_CONTROL 0x42 274#define CRT_ID_EXT_MODE 0x43 275#define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 276#define CRT_ID_HWGC_ORIGIN_X_HI 0x46 277#define CRT_ID_HWGC_ORIGIN_X_LO 0x47 278#define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 279#define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 280#define CRT_ID_HWGC_FG_STACK 0x4A 281#define CRT_ID_HWGC_BG_STACK 0x4B 282#define CRT_ID_HWGC_START_AD_HI 0x4C 283#define CRT_ID_HWGC_START_AD_LO 0x4D 284#define CRT_ID_HWGC_DSTART_X 0x4E 285#define CRT_ID_HWGC_DSTART_Y 0x4F 286/* S3 extensions: System Extension Registers */ 287#define CRT_ID_EXT_SYS_CNTL_1 0x50 288#define CRT_ID_EXT_SYS_CNTL_2 0x51 289#define CRT_ID_EXT_BIOS_FLAG_1 0x52 290#define CRT_ID_EXT_MEM_CNTL_1 0x53 291#define CRT_ID_EXT_MEM_CNTL_2 0x54 292#define CRT_ID_EXT_DAC_CNTL 0x55 293#define CRT_ID_EX_SYNC_1 0x56 294#define CRT_ID_EX_SYNC_2 0x57 295#define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 296#define CRT_ID_LAW_POS_HI 0x59 297#define CRT_ID_LAW_POS_LO 0x5A 298#define CRT_ID_GOUT_PORT 0x5C 299#define CRT_ID_EXT_HOR_OVF 0x5D 300#define CRT_ID_EXT_VER_OVF 0x5E 301#define CRT_ID_EXT_MEM_CNTL_3 0x60 302#define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */ 303#define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */ 304#define CRT_ID_EXT_MISC_CNTL 0x65 305#define CRT_ID_EXT_MISC_CNTL_1 0x66 306#define CRT_ID_EXT_MISC_CNTL_2 0x67 307#define CRT_ID_CONFIG_3 0x68 308#define CRT_ID_EXT_SYS_CNTL_3 0x69 309#define CRT_ID_EXT_SYS_CNTL_4 0x6A 310#define CRT_ID_EXT_BIOS_FLAG_3 0x6B 311#define CRT_ID_EXT_BIOS_FLAG_4 0x6C 312#define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */ 313#define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */ 314#define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */ 315 316/* Streams Processor */ 317#define SP_PRIMARY_CONTROL 0x8180 318#define SP_COLOR_CHROMA_KEY_CONTROL 0x8184 319#define SP_SECONDARY_CONTROL 0x8190 320#define SP_CHROMA_KEY_UPPER_BOUND 0x8194 321#define SP_SECONDARY_CONSTANTS 0x8198 322#define SP_BLEND_CONTROL 0x81A0 323#define SP_PRIMARY_ADDRESS_0 0x81C0 324#define SP_PRIMARY_ADDRESS_1 0x81C4 325#define SP_PRIMARY_STRIDE 0x81C8 326#define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC 327#define SP_SECONDARY_ADDRESS_0 0x81D0 328#define SP_SECONDARY_ADDRESS_1 0x81D4 329#define SP_SECONDARY_STRIDE 0x81D8 330#define SP_OPAQUE_OVERLAY_CONTROL 0x81DC 331#define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0 332#define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4 333#define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8 334#define SP_FIFO_CONTROL 0x81EC 335#define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0 336#define SP_PRIMARY_WINDOW_SIZE 0x81F4 337#define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8 338#define SP_SECONDARY_WINDOW_SIZE 0x81FC 339 340/* Memory Port Controller */ 341#define MPC_FIFO_CONTROL 0x8200 342#define MPC_MIU_CONTROL 0x8204 343#define MPC_STREAMS_TIMEOUT 0x8208 344#define MPC_MISC_TIMEOUT 0x820C 345#define MPC_DMA_READ_BASE_ADDRESS 0x8220 346#define MPC_DMA_READ_STRIDE_WIDTH 0x8224 347 348/* Miscellaneous Registers */ 349#define MR_SUBSYSTEM_STATUS_CNTL 0x8504 350#define MR_ADVANCED_FUNCTION_CONTROL 0x850C 351 352/* S3d Engine */ 353#define S3D_BIT_BLT_RECT_FILL 0xA400 354#define S3D_LINE_2D 0xA800 355#define S3D_POLYGON_2D 0xAC00 356#define S3D_LINE_3D 0xB000 357#define S3D_TRIANGLE_3D 0xB400 358 359#define BLT_ADDRESS 0xA4D4 360#define BLT_SOURCE_ADDRESS 0xA4D4 361#define BLT_DEST_ADDRESS 0xA4D8 362#define BLT_CLIP_LEFT_RIGHT 0xA4DC 363#define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT 364#define BLT_CLIP_RIGHT 0xA4DE 365#define BLT_CLIP_TOP_BOTTOM 0xA4E0 366#define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM 367#define BLT_CLIP_TOP 0xA4E2 368#define BLT_DEST_SOURCE_PITCH 0xA4E4 369#define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH 370#define BLT_DEST_PITCH 0xA4E6 371#define BLT_MONO_PATTERN 0xA4E8 372#define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN 373#define BLT_MONO_PATTERN_1 0xA4EC 374#define BLT_PATTERN_BG_COLOR 0xA4F0 375#define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR 376#define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR 377#define BLT_PATTERN_BG_COLOR_RED 0xA4F1 378#define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2 379#define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR 380#define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3 381#define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX 382#define BLT_PATTERN_FG_COLOR 0xA4F4 383#define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR 384#define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR 385#define BLT_PATTERN_FG_COLOR_RED 0xA4F5 386#define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6 387#define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR 388#define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7 389#define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX 390#define BLT_SOURCE_BG_COLOR 0xA4F8 391#define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR 392#define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR 393#define BLT_SOURCE_BG_COLOR_RED 0xA4F9 394#define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA 395#define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR 396#define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB 397#define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX 398#define BLT_SOURCE_FG_COLOR 0xA4FC 399#define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR 400#define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR 401#define BLT_SOURCE_FG_COLOR_RED 0xA4FD 402#define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE 403#define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR 404#define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF 405#define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX 406#define BLT_COMMAND_SET 0xA500 407#define BLT_WIDTH_HEIGHT 0xA504 408#define BLT_HEIGHT BLT_WIDTH_HEIGHT 409#define BLT_WIDTH 0xA506 410#define BLT_SOURCE_XY 0xA508 411#define BLT_SOURCE_Y BLT_SOURCE_XY 412#define BLT_SOURCE_X 0xA50A 413#define BLT_DESTINATION_XY 0xA50C 414#define BLT_DESTINATION_Y BLT_DESTINATION_XY 415#define BLT_DESTINATION_X 0xA50E 416 417#define L2D_ADDRESS 0xA8D4 418#define L2D_SOURCE_ADDRESS 0xA8D4 419#define L2D_DEST_ADDRESS 0xA8D8 420#define L2D_CLIP_LEFT_RIGHT 0xA8DC 421#define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT 422#define L2D_CLIP_RIGHT 0xA8DE 423#define L2D_CLIP_TOP_BOTTOM 0xA8E0 424#define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM 425#define L2D_CLIP_TOP 0xA8E2 426#define L2D_DEST_SOURCE_PITCH 0xA8E4 427#define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH 428#define L2D_DEST_PITCH 0xA8E6 429#define L2D_PAD_0 0xA8E8 430#define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4 431#define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR 432#define L2D_PATTERN_FG_COLOR_RED 0xA8F5 433#define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6 434#define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR 435#define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7 436#define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX 437#define L2D_PAD_1 0xA8F8 438#define L2D_COMMAND_SET 0xA900 439#define L2D_PAD_2 0xA904 440#define L2D_END_0_END_1 0xA96C 441#define L2D_END_1 L2D_END_0_END_1 442#define L2D_END_0 0xA96E 443#define L2D_DX 0xA970 444#define L2D_X_START 0xA974 445#define L2D_Y_START 0xA978 446#define L2D_Y_COUNT 0xA97C 447 448#define P2D_ADDRESS 0xACD4 449#define P2D_SOURCE_ADDRESS 0xACD4 450#define P2D_DEST_ADDRESS 0xACD8 451#define P2D_CLIP_LEFT_RIGHT 0xACDC 452#define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT 453#define P2D_CLIP_RIGHT 0xACDE 454#define P2D_CLIP_TOP_BOTTOM 0xACE0 455#define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM 456#define P2D_CLIP_TOP 0xACE2 457#define P2D_DEST_SOURCE_PITCH 0xACE4 458#define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH 459#define P2D_DEST_PITCH 0xACE6 460#define P2D_MONO_PATTERN 0xACE8 461#define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0 462#define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR 463#define P2D_PATTERN_BG_COLOR_RED 0xACF1 464#define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2 465#define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR 466#define P2D_PATTERN_BG_COLOR_INDEX 0xACF3 467#define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX 468#define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4 469#define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR 470#define P2D_PATTERN_FG_COLOR_RED 0xACF5 471#define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6 472#define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR 473#define P2D_PATTERN_FG_COLOR_INDEX 0xACF7 474#define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX 475#define P2D_PAD_1 0xACF8 476#define P2D_COMMAND_SET 0xAD00 477#define P2D_PAD_2 0xAD04 478#define P2D_RIGHT_DX 0xAD68 479#define P2D_RIGHT_X_START 0xAD6C 480#define P2D_LEFT_DX 0xAD70 481#define P2D_LEFT_X_START 0xAD74 482#define P2D_Y_START 0xAD78 483#define P2D_Y_COUNT 0xAD7C 484 485#define CMD_NOP (7 << 27) /* %1111 << 27 */ 486#define CMD_LINE (3 << 27) /* %0011 << 27 */ 487#define CMD_RECT (4 << 27) /* %0010 << 27 */ 488#define CMD_POLYGON (5 << 27) /* %0101 << 27 */ 489#define CMD_BITBLT (0 << 27) /* %0000 << 27 */ 490 491#define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */ 492#define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */ 493#define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */ 494 495#define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */ 496#define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */ 497#define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */ 498 499#define CMD_CHUNKY (0 << 2) /* %00 << 2 */ 500#define CMD_HI_COLOR (1 << 2) /* %01 << 2 */ 501#define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */ 502 503#define ROP_FALSE 0x00 504#define ROP_NOR 0x10 505#define ROP_ONLYDST 0x20 506#define ROP_NOTSRC 0x30 507#define ROP_ONLYSRC 0x40 508#define ROP_NOTDST 0x50 509#define ROP_EOR 0x60 510#define ROP_NAND 0x70 511#define ROP_AND 0x80 512#define ROP_NEOR 0x90 513#define ROP_DST 0xA0 514#define ROP_NOTONLYSRC 0xB0 515#define ROP_SRC 0xC0 516#define ROP_NOTONLYDST 0xD0 517#define ROP_OR 0xE0 518#define ROP_TRUE 0xF0 519 520/* Pass-through */ 521#if 0 /* XXX */ 522#define PASS_ADDRESS 0x 523#define PASS_ADDRESS_W 0x 524#endif 525 526/* Video DAC */ 527#define VDAC_ADDRESS 0x03C8 528#define VDAC_ADDRESS_W 0x03C8 529#define VDAC_ADDRESS_R 0x03C7 530#define VDAC_STATE 0x03C7 531#define VDAC_DATA 0x03C9 532#define VDAC_MASK 0x03C6 533 534 535#define WGfx(ba, idx, val) \ 536 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 537 538#define WSeq(ba, idx, val) \ 539 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 540 541#define WCrt(ba, idx, val) \ 542 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 543 544#define WAttr(ba, idx, val) \ 545 do { \ 546 unsigned char tmp;\ 547 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 548 vgaw(ba, ACT_ADDRESS_W, idx);\ 549 vgaw(ba, ACT_ADDRESS_W, val);\ 550 } while (0) 551 552 553#define SetTextPlane(ba, m) \ 554 do { \ 555 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 556 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 557 } while (0) 558 559 560/* Gfx engine busy wait */ 561 562static inline void 563GfxBusyWait (ba) 564 volatile void *ba; 565{ 566 int test; 567 568 do { 569 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 570 __asm volatile ("nop"); 571 } while (!(test & (1 << 13))); 572} 573 574 575static inline void 576GfxFifoWait(ba) 577 volatile void *ba; 578{ 579#if 0 /* XXX */ 580 int test; 581 582 do { 583 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 584 } while (test & 0x0f); 585#endif 586} 587 588 589/* Special wakeup/passthrough registers on graphics boards 590 * 591 * The methods have diverged a bit for each board, so 592 * WPass(P) has been converted into a set of specific 593 * inline functions. 594 */ 595 596static inline unsigned char 597RAttr(ba, idx) 598 volatile void *ba; 599 short idx; 600{ 601 602 vgaw(ba, ACT_ADDRESS_W, idx); 603 delay(0); 604 return vgar(ba, ACT_ADDRESS_R); 605} 606 607static inline unsigned char 608RSeq(ba, idx) 609 volatile void *ba; 610 short idx; 611{ 612 vgaw(ba, SEQ_ADDRESS, idx); 613 return vgar(ba, SEQ_ADDRESS_R); 614} 615 616static inline unsigned char 617RCrt(ba, idx) 618 volatile void *ba; 619 short idx; 620{ 621 vgaw(ba, CRT_ADDRESS, idx); 622 return vgar(ba, CRT_ADDRESS_R); 623} 624 625static inline unsigned char 626RGfx(ba, idx) 627 volatile void *ba; 628 short idx; 629{ 630 vgaw(ba, GCT_ADDRESS, idx); 631 return vgar(ba, GCT_ADDRESS_R); 632} 633 634#endif /* _GRF_CV3DREG_H */ 635