119872Swollman/* $NetBSD: grf_cv3dreg.h,v 1.13 2016/06/17 07:41:56 phx Exp $ */ 219872Swollman 319872Swollman/* 419872Swollman * Copyright (c) 1995 Michael Teske 519872Swollman * All rights reserved. 619872Swollman * 719872Swollman * Redistribution and use in source and binary forms, with or without 819872Swollman * modification, are permitted provided that the following conditions 919872Swollman * are met: 1019872Swollman * 1. Redistributions of source code must retain the above copyright 1119872Swollman * notice, this list of conditions and the following disclaimer. 1219872Swollman * 2. Redistributions in binary form must reproduce the above copyright 1319872Swollman * notice, this list of conditions and the following disclaimer in the 1419872Swollman * documentation and/or other materials provided with the distribution. 15179530Sjkim * 3. All advertising materials mentioning features or use of this software 1619872Swollman * must display the following acknowledgement: 1719872Swollman * This product includes software developed by Ezra Story and by Kari 1819872Swollman * Mettinen. 1919872Swollman * 4. The name of the author may not be used to endorse or promote products 2019872Swollman * derived from this software without specific prior written permission 2119872Swollman * 2219872Swollman * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2319872Swollman * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2419872Swollman * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2519872Swollman * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2619872Swollman * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2719872Swollman * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2819872Swollman * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2919872Swollman * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3019872Swollman * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3119872Swollman * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3219872Swollman */ 3319872Swollman 3419872Swollman#ifndef _GRF_CV3DREG_H 35179530Sjkim#define _GRF_CV3DREG_H 36179530Sjkim 3730763Scharnier/* 3819872Swollman * This is derived from Cirrus driver source. 3919872Swollman */ 4019872Swollman 4119872Swollman/* Extension to grfvideo_mode to support text modes. 4219872Swollman * This can be passed to both text & gfx functions 4366907Swollman * without worry. If gv.depth == 4, then the extended 4419872Swollman * fields for a text mode are present. 4519872Swollman */ 4619872Swollman 47198267Sedwinstruct grfcv3dtext_mode { 4819872Swollman struct grfvideo_mode gv; 4919872Swollman unsigned short fx; /* font x dimension */ 50274394Sdteske unsigned short fy; /* font y dimension */ 5119872Swollman unsigned short cols; /* screen dimensions */ 52227934Sfjoe unsigned short rows; 53227934Sfjoe void *fdata; /* font data */ 54179530Sjkim unsigned short fdstart; 55179530Sjkim unsigned short fdend; 56179530Sjkim}; 57179530Sjkim 58198267Sedwin/* read VGA register */ 59179530Sjkim#define vgar(ba, reg) \ 6019872Swollman *(((volatile char *)ba)+(reg ^ 3)) 61230005Swollman 62230005Swollman/* write VGA register */ 63230005Swollman#define vgaw(ba, reg, val) \ 64230005Swollman *(((volatile char *)ba)+(reg ^ 3)) = ((val) & 0xff) 65230005Swollman 66230005Swollman/* MMIO access */ 67230005Swollman#define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) ) 68227934Sfjoe 69227934Sfjoe#define vgario(ba, reg) \ 70227934Sfjoe *(((volatile char *)ba) + ( ByteAccessIO(reg) )) 71227934Sfjoe 72227934Sfjoe#define vgawio(ba, reg, val) \ 73227934Sfjoe do { \ 74227934Sfjoe if (!cv3d_zorroIII) { \ 75227934Sfjoe *(((volatile char *)cv3d_vcode_switch_base) + \ 76227934Sfjoe 0x04) = (0x01 & 0xffff); \ 77227934Sfjoe __asm volatile ("nop"); \ 78227934Sfjoe } \ 79227934Sfjoe *(((volatile char *)cv3d_special_register_base) + \ 80227934Sfjoe ( ByteAccessIO(reg) & 0xffff )) = ((val) & 0xff); \ 81227934Sfjoe if (!cv3d_zorroIII) { \ 82227934Sfjoe *(((volatile char *)cv3d_vcode_switch_base) + \ 83227934Sfjoe 0x04) = (0x02 & 0xffff); \ 84228176Sfjoe __asm volatile ("nop"); \ 85228176Sfjoe } \ 86228176Sfjoe } while (0) 87228176Sfjoe 88228176Sfjoe/* read 32 Bit VGA register */ 89228176Sfjoe#define vgar32(ba, reg) \ 90228176Sfjoe *((volatile unsigned long *) (((volatile char *)ba)+reg)) 91228176Sfjoe 92228176Sfjoe/* write 32 Bit VGA register */ 93228176Sfjoe#define vgaw32(ba, reg, val) \ 94228176Sfjoe *((volatile unsigned long *) (((volatile char *)ba)+reg)) = val 95228176Sfjoe 96228176Sfjoe/* read 16 Bit VGA register */ 97228176Sfjoe#define vgar16(ba, reg) \ 98228176Sfjoe *((volatile unsigned short *) (((volatile char *)ba)+reg)) 99228176Sfjoe 100228176Sfjoe/* write 16 Bit VGA register */ 101228176Sfjoe#define vgaw16(ba, reg, val) \ 102228176Sfjoe *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val 103228176Sfjoe 104228176Sfjoe#define Select_Zorro2_FrameBuffer(flag) \ 105228176Sfjoe do { \ 106228176Sfjoe *(((volatile char *)cv3d_vcode_switch_base) + \ 107228176Sfjoe 0x08) = ((flag * 0x40) & 0xffff); \ 108228176Sfjoe __asm volatile ("nop"); \ 109228176Sfjoe} while (0) 110228176Sfjoe 111228176Sfjoeint grfcv3d_cnprobe(void); 112228176Sfjoevoid grfcv3d_iteinit(struct grf_softc *); 113228176Sfjoestatic inline void GfxBusyWait(volatile void *); 114228176Sfjoestatic inline void GfxFifoWait(volatile void *); 115228176Sfjoestatic inline unsigned char RAttr(volatile void *, short); 116227934Sfjoestatic inline unsigned char RSeq(volatile void *, short); 117227934Sfjoestatic inline unsigned char RCrt(volatile void *, short); 118227934Sfjoestatic inline unsigned char RGfx(volatile void *, short); 119227947Sfjoe 120227934Sfjoe 121227934Sfjoe/* 122227934Sfjoe * defines for the used register addresses (mw) 123227934Sfjoe * 124227934Sfjoe * NOTE: there are some registers that have different addresses when 125227934Sfjoe * in mono or color mode. We only support color mode, and thus 126227947Sfjoe * some addresses won't work in mono-mode! 127227934Sfjoe * 128227934Sfjoe * General and VGA-registers taken from retina driver. Fixed a few 129227934Sfjoe * bugs in it. (SR and GR read address is Port + 1, NOT Port) 130227934Sfjoe * 131227934Sfjoe */ 132227934Sfjoe 133228176Sfjoe/* General Registers: */ 134228176Sfjoe#define GREG_MISC_OUTPUT_R 0x03CC 135228176Sfjoe#define GREG_MISC_OUTPUT_W 0x03C2 136228176Sfjoe#define GREG_FEATURE_CONTROL_R 0x03CA 137228176Sfjoe#define GREG_FEATURE_CONTROL_W 0x03DA 138228176Sfjoe#define GREG_INPUT_STATUS0_R 0x03C2 139227934Sfjoe#define GREG_INPUT_STATUS1_R 0x03DA 140227934Sfjoe 141227934Sfjoe/* Setup Registers: */ 142227934Sfjoe#define SREG_OPTION_SELECT 0x0102 143227934Sfjoe#define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */ 144227934Sfjoe 145227934Sfjoe/* Attribute Controller: */ 146227934Sfjoe#define ACT_ADDRESS 0x03C0 147227934Sfjoe#define ACT_ADDRESS_R 0x03C1 148227934Sfjoe#define ACT_ADDRESS_W 0x03C0 149227934Sfjoe#define ACT_ADDRESS_RESET 0x03DA 150227934Sfjoe#define ACT_ID_PALETTE0 0x00 151227934Sfjoe#define ACT_ID_PALETTE1 0x01 152228176Sfjoe#define ACT_ID_PALETTE2 0x02 153227934Sfjoe#define ACT_ID_PALETTE3 0x03 154227934Sfjoe#define ACT_ID_PALETTE4 0x04 155227934Sfjoe#define ACT_ID_PALETTE5 0x05 156227934Sfjoe#define ACT_ID_PALETTE6 0x06 157227934Sfjoe#define ACT_ID_PALETTE7 0x07 158227934Sfjoe#define ACT_ID_PALETTE8 0x08 159227934Sfjoe#define ACT_ID_PALETTE9 0x09 160227947Sfjoe#define ACT_ID_PALETTE10 0x0A 161227934Sfjoe#define ACT_ID_PALETTE11 0x0B 162227934Sfjoe#define ACT_ID_PALETTE12 0x0C 163227934Sfjoe#define ACT_ID_PALETTE13 0x0D 164227934Sfjoe#define ACT_ID_PALETTE14 0x0E 165227934Sfjoe#define ACT_ID_PALETTE15 0x0F 166227934Sfjoe#define ACT_ID_ATTR_MODE_CNTL 0x10 167227934Sfjoe#define ACT_ID_OVERSCAN_COLOR 0x11 168227934Sfjoe#define ACT_ID_COLOR_PLANE_ENA 0x12 169227934Sfjoe#define ACT_ID_HOR_PEL_PANNING 0x13 170227934Sfjoe#define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */ 171227934Sfjoe 172227934Sfjoe/* Graphics Controller: */ 173227934Sfjoe#define GCT_ADDRESS 0x03CE 174227934Sfjoe#define GCT_ADDRESS_R 0x03CF 175227934Sfjoe#define GCT_ADDRESS_W 0x03CF 176227934Sfjoe#define GCT_ID_SET_RESET 0x00 177227934Sfjoe#define GCT_ID_ENABLE_SET_RESET 0x01 178227934Sfjoe#define GCT_ID_COLOR_COMPARE 0x02 179227934Sfjoe#define GCT_ID_DATA_ROTATE 0x03 180227934Sfjoe#define GCT_ID_READ_MAP_SELECT 0x04 181227934Sfjoe#define GCT_ID_GRAPHICS_MODE 0x05 182227934Sfjoe#define GCT_ID_MISC 0x06 183227934Sfjoe#define GCT_ID_COLOR_XCARE 0x07 184227934Sfjoe#define GCT_ID_BITMASK 0x08 185227934Sfjoe 186227934Sfjoe/* Sequencer: */ 187227934Sfjoe#define SEQ_ADDRESS 0x03C4 188227934Sfjoe#define SEQ_ADDRESS_R 0x03C5 189227934Sfjoe#define SEQ_ADDRESS_W 0x03C5 190198350Sedwin#define SEQ_ID_RESET 0x00 191227934Sfjoe#define SEQ_ID_CLOCKING_MODE 0x01 192198350Sedwin#define SEQ_ID_MAP_MASK 0x02 193198350Sedwin#define SEQ_ID_CHAR_MAP_SELECT 0x03 19419872Swollman#define SEQ_ID_MEMORY_MODE 0x04 195198267Sedwin#define SEQ_ID_UNKNOWN1 0x05 196198350Sedwin#define SEQ_ID_UNKNOWN2 0x06 197198350Sedwin#define SEQ_ID_UNKNOWN3 0x07 19819872Swollman/* S3 extensions */ 199179530Sjkim#define SEQ_ID_UNLOCK_EXT 0x08 200220172Sedwin#define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */ 201179530Sjkim#define SEQ_ID_BUS_REQ_CNTL 0x0A 202301131Ssmh#define SEQ_ID_EXT_MISC_SEQ 0x0B 203220172Sedwin#define SEQ_ID_UNKNOWN4 0x0C 204179530Sjkim#define SEQ_ID_EXT_SEQ 0x0D 205179530Sjkim#define SEQ_ID_UNKNOWN5 0x0E 206179530Sjkim#define SEQ_ID_UNKNOWN6 0x0F 207220172Sedwin#define SEQ_ID_MCLK_LO 0x10 20819872Swollman#define SEQ_ID_MCLK_HI 0x11 20919872Swollman#define SEQ_ID_DCLK_LO 0x12 21019872Swollman#define SEQ_ID_DCLK_HI 0x13 211179530Sjkim#define SEQ_ID_CLKSYN_CNTL_1 0x14 21219872Swollman#define SEQ_ID_CLKSYN_CNTL_2 0x15 21319872Swollman#define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 214179530Sjkim#define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 215220172Sedwin#define SEQ_ID_RAMDAC_CNTL 0x18 21619872Swollman#define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */ 21719872Swollman#define SEQ_ID_SIGNAL_SELECT 0x1C 218179530Sjkim 21919872Swollman/* CRT Controller: */ 22019872Swollman#define CRT_ADDRESS 0x03D4 221179530Sjkim#define CRT_ADDRESS_R 0x03D5 222179530Sjkim#define CRT_ADDRESS_W 0x03D5 223179530Sjkim#define CRT_ID_HOR_TOTAL 0x00 224179530Sjkim#define CRT_ID_HOR_DISP_ENA_END 0x01 225179530Sjkim#define CRT_ID_START_HOR_BLANK 0x02 226179530Sjkim#define CRT_ID_END_HOR_BLANK 0x03 227179530Sjkim#define CRT_ID_START_HOR_RETR 0x04 228179530Sjkim#define CRT_ID_END_HOR_RETR 0x05 229179530Sjkim#define CRT_ID_VER_TOTAL 0x06 230220172Sedwin#define CRT_ID_OVERFLOW 0x07 231227934Sfjoe#define CRT_ID_PRESET_ROW_SCAN 0x08 23219872Swollman#define CRT_ID_MAX_SCAN_LINE 0x09 23319872Swollman#define CRT_ID_CURSOR_START 0x0A 234179530Sjkim#define CRT_ID_CURSOR_END 0x0B 235179530Sjkim#define CRT_ID_START_ADDR_HIGH 0x0C 236179530Sjkim#define CRT_ID_START_ADDR_LOW 0x0D 237179530Sjkim#define CRT_ID_CURSOR_LOC_HIGH 0x0E 238179530Sjkim#define CRT_ID_CURSOR_LOC_LOW 0x0F 239179530Sjkim#define CRT_ID_START_VER_RETR 0x10 240179530Sjkim#define CRT_ID_END_VER_RETR 0x11 241179530Sjkim#define CRT_ID_VER_DISP_ENA_END 0x12 242179530Sjkim#define CRT_ID_SCREEN_OFFSET 0x13 243179530Sjkim#define CRT_ID_UNDERLINE_LOC 0x14 244179530Sjkim#define CRT_ID_START_VER_BLANK 0x15 245179530Sjkim#define CRT_ID_END_VER_BLANK 0x16 246179530Sjkim#define CRT_ID_MODE_CONTROL 0x17 247220172Sedwin#define CRT_ID_LINE_COMPARE 0x18 248220172Sedwin#define CRT_ID_GD_LATCH_RBACK 0x22 24919872Swollman#define CRT_ID_ACT_TOGGLE_RBACK 0x24 25019872Swollman#define CRT_ID_ACT_INDEX_RBACK 0x26 251179530Sjkim/* S3 extensions: S3 VGA Registers */ 252179530Sjkim#define CRT_ID_DEVICE_HIGH 0x2D 253179530Sjkim#define CRT_ID_DEVICE_LOW 0x2E 254179530Sjkim#define CRT_ID_REVISION 0x2F 255179530Sjkim#define CRT_ID_CHIP_ID_REV 0x30 256179530Sjkim#define CRT_ID_MEMORY_CONF 0x31 25719872Swollman#define CRT_ID_BACKWAD_COMP_1 0x32 25819872Swollman#define CRT_ID_BACKWAD_COMP_2 0x33 25919872Swollman#define CRT_ID_BACKWAD_COMP_3 0x34 260179530Sjkim#define CRT_ID_REGISTER_LOCK 0x35 26119872Swollman#define CRT_ID_CONFIG_1 0x36 262179530Sjkim#define CRT_ID_CONFIG_2 0x37 263179530Sjkim#define CRT_ID_REGISTER_LOCK_1 0x38 264179530Sjkim#define CRT_ID_REGISTER_LOCK_2 0x39 26519872Swollman#define CRT_ID_MISC_1 0x3A 266220172Sedwin#define CRT_ID_DISPLAY_FIFO 0x3B 267227934Sfjoe#define CRT_ID_LACE_RETR_START 0x3C 268220172Sedwin/* S3 extensions: System Control Registers */ 26919872Swollman#define CRT_ID_SYSTEM_CONFIG 0x40 270179497Sjkim#define CRT_ID_BIOS_FLAG 0x41 271179497Sjkim#define CRT_ID_LACE_CONTROL 0x42 27219872Swollman#define CRT_ID_EXT_MODE 0x43 27319872Swollman#define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 274179530Sjkim#define CRT_ID_HWGC_ORIGIN_X_HI 0x46 275179530Sjkim#define CRT_ID_HWGC_ORIGIN_X_LO 0x47 276179530Sjkim#define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 277179530Sjkim#define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 278179530Sjkim#define CRT_ID_HWGC_FG_STACK 0x4A 279179530Sjkim#define CRT_ID_HWGC_BG_STACK 0x4B 280179530Sjkim#define CRT_ID_HWGC_START_AD_HI 0x4C 281179530Sjkim#define CRT_ID_HWGC_START_AD_LO 0x4D 282179530Sjkim#define CRT_ID_HWGC_DSTART_X 0x4E 28319872Swollman#define CRT_ID_HWGC_DSTART_Y 0x4F 28419872Swollman/* S3 extensions: System Extension Registers */ 285227934Sfjoe#define CRT_ID_EXT_SYS_CNTL_1 0x50 286227934Sfjoe#define CRT_ID_EXT_SYS_CNTL_2 0x51 28719872Swollman#define CRT_ID_EXT_BIOS_FLAG_1 0x52 288179530Sjkim#define CRT_ID_EXT_MEM_CNTL_1 0x53 289179530Sjkim#define CRT_ID_EXT_MEM_CNTL_2 0x54 29019872Swollman#define CRT_ID_EXT_DAC_CNTL 0x55 29119872Swollman#define CRT_ID_EX_SYNC_1 0x56 29219872Swollman#define CRT_ID_EX_SYNC_2 0x57 29319872Swollman#define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 29419872Swollman#define CRT_ID_LAW_POS_HI 0x59 295179530Sjkim#define CRT_ID_LAW_POS_LO 0x5A 29619872Swollman#define CRT_ID_GOUT_PORT 0x5C 297179530Sjkim#define CRT_ID_EXT_HOR_OVF 0x5D 29819872Swollman#define CRT_ID_EXT_VER_OVF 0x5E 299179530Sjkim#define CRT_ID_EXT_MEM_CNTL_3 0x60 300179530Sjkim#define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */ 30119872Swollman#define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */ 30219872Swollman#define CRT_ID_EXT_MISC_CNTL 0x65 30319872Swollman#define CRT_ID_EXT_MISC_CNTL_1 0x66 304179530Sjkim#define CRT_ID_EXT_MISC_CNTL_2 0x67 305179530Sjkim#define CRT_ID_CONFIG_3 0x68 306179530Sjkim#define CRT_ID_EXT_SYS_CNTL_3 0x69 307179530Sjkim#define CRT_ID_EXT_SYS_CNTL_4 0x6A 308179530Sjkim#define CRT_ID_EXT_BIOS_FLAG_3 0x6B 309179530Sjkim#define CRT_ID_EXT_BIOS_FLAG_4 0x6C 310179530Sjkim#define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */ 31119872Swollman#define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */ 31219872Swollman#define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */ 31319872Swollman 31460938Sjake/* Streams Processor */ 315179530Sjkim#define SP_PRIMARY_CONTROL 0x8180 316179530Sjkim#define SP_COLOR_CHROMA_KEY_CONTROL 0x8184 31719872Swollman#define SP_SECONDARY_CONTROL 0x8190 31819872Swollman#define SP_CHROMA_KEY_UPPER_BOUND 0x8194 31919872Swollman#define SP_SECONDARY_CONSTANTS 0x8198 32019872Swollman#define SP_BLEND_CONTROL 0x81A0 32119872Swollman#define SP_PRIMARY_ADDRESS_0 0x81C0 32219872Swollman#define SP_PRIMARY_ADDRESS_1 0x81C4 32319872Swollman#define SP_PRIMARY_STRIDE 0x81C8 32419872Swollman#define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC 325179530Sjkim#define SP_SECONDARY_ADDRESS_0 0x81D0 32622181Sjhay#define SP_SECONDARY_ADDRESS_1 0x81D4 32719872Swollman#define SP_SECONDARY_STRIDE 0x81D8 328179530Sjkim#define SP_OPAQUE_OVERLAY_CONTROL 0x81DC 329179530Sjkim#define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0 33019872Swollman#define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4 33119872Swollman#define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8 33219872Swollman#define SP_FIFO_CONTROL 0x81EC 33319872Swollman#define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0 33419872Swollman#define SP_PRIMARY_WINDOW_SIZE 0x81F4 33519872Swollman#define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8 33619872Swollman#define SP_SECONDARY_WINDOW_SIZE 0x81FC 337179530Sjkim 338179530Sjkim/* Memory Port Controller */ 339179530Sjkim#define MPC_FIFO_CONTROL 0x8200 340179530Sjkim#define MPC_MIU_CONTROL 0x8204 341179530Sjkim#define MPC_STREAMS_TIMEOUT 0x8208 34219872Swollman#define MPC_MISC_TIMEOUT 0x820C 343198350Sedwin#define MPC_DMA_READ_BASE_ADDRESS 0x8220 34419872Swollman#define MPC_DMA_READ_STRIDE_WIDTH 0x8224 345209190Semaste 34619872Swollman/* Miscellaneous Registers */ 34719872Swollman#define MR_SUBSYSTEM_STATUS_CNTL 0x8504 348298033Saraujo#define MR_ADVANCED_FUNCTION_CONTROL 0x850C 34919872Swollman 35019872Swollman/* S3d Engine */ 351198350Sedwin#define S3D_BIT_BLT_RECT_FILL 0xA400 35219872Swollman#define S3D_LINE_2D 0xA800 35330999Sjoerg#define S3D_POLYGON_2D 0xAC00 35419872Swollman#define S3D_LINE_3D 0xB000 35519872Swollman#define S3D_TRIANGLE_3D 0xB400 35619872Swollman 35719872Swollman#define BLT_ADDRESS 0xA4D4 358298033Saraujo#define BLT_SOURCE_ADDRESS 0xA4D4 359198350Sedwin#define BLT_DEST_ADDRESS 0xA4D8 36019872Swollman#define BLT_CLIP_LEFT_RIGHT 0xA4DC 361198350Sedwin#define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT 362179530Sjkim#define BLT_CLIP_RIGHT 0xA4DE 36319872Swollman#define BLT_CLIP_TOP_BOTTOM 0xA4E0 36419872Swollman#define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM 365179530Sjkim#define BLT_CLIP_TOP 0xA4E2 366298033Saraujo#define BLT_DEST_SOURCE_PITCH 0xA4E4 367198350Sedwin#define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH 368179530Sjkim#define BLT_DEST_PITCH 0xA4E6 369298033Saraujo#define BLT_MONO_PATTERN 0xA4E8 370198350Sedwin#define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN 37119872Swollman#define BLT_MONO_PATTERN_1 0xA4EC 37219872Swollman#define BLT_PATTERN_BG_COLOR 0xA4F0 37319872Swollman#define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR 37419872Swollman#define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR 37519872Swollman#define BLT_PATTERN_BG_COLOR_RED 0xA4F1 376198350Sedwin#define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2 377198350Sedwin#define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR 37819872Swollman#define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3 37956487Scharnier#define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX 38056487Scharnier#define BLT_PATTERN_FG_COLOR 0xA4F4 38119872Swollman#define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR 38256487Scharnier#define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR 38356487Scharnier#define BLT_PATTERN_FG_COLOR_RED 0xA4F5 38419872Swollman#define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6 38519872Swollman#define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR 38619872Swollman#define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7 38719872Swollman#define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX 38819872Swollman#define BLT_SOURCE_BG_COLOR 0xA4F8 38919872Swollman#define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR 39019872Swollman#define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR 391179530Sjkim#define BLT_SOURCE_BG_COLOR_RED 0xA4F9 39219872Swollman#define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA 393179530Sjkim#define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR 394179530Sjkim#define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB 39519872Swollman#define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX 39619872Swollman#define BLT_SOURCE_FG_COLOR 0xA4FC 397198350Sedwin#define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR 398179530Sjkim#define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR 399227934Sfjoe#define BLT_SOURCE_FG_COLOR_RED 0xA4FD 40019872Swollman#define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE 40119872Swollman#define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR 402198350Sedwin#define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF 403179530Sjkim#define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX 40419872Swollman#define BLT_COMMAND_SET 0xA500 40519872Swollman#define BLT_WIDTH_HEIGHT 0xA504 40619872Swollman#define BLT_HEIGHT BLT_WIDTH_HEIGHT 407198350Sedwin#define BLT_WIDTH 0xA506 408198350Sedwin#define BLT_SOURCE_XY 0xA508 40919872Swollman#define BLT_SOURCE_Y BLT_SOURCE_XY 410179530Sjkim#define BLT_SOURCE_X 0xA50A 411298033Saraujo#define BLT_DESTINATION_XY 0xA50C 412179530Sjkim#define BLT_DESTINATION_Y BLT_DESTINATION_XY 413227934Sfjoe#define BLT_DESTINATION_X 0xA50E 41419872Swollman 41519872Swollman#define L2D_ADDRESS 0xA8D4 41619872Swollman#define L2D_SOURCE_ADDRESS 0xA8D4 41719872Swollman#define L2D_DEST_ADDRESS 0xA8D8 41856487Scharnier#define L2D_CLIP_LEFT_RIGHT 0xA8DC 41956487Scharnier#define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT 42019872Swollman#define L2D_CLIP_RIGHT 0xA8DE 42156487Scharnier#define L2D_CLIP_TOP_BOTTOM 0xA8E0 42256487Scharnier#define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM 42319872Swollman#define L2D_CLIP_TOP 0xA8E2 42419872Swollman#define L2D_DEST_SOURCE_PITCH 0xA8E4 42519872Swollman#define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH 42619872Swollman#define L2D_DEST_PITCH 0xA8E6 42719872Swollman#define L2D_PAD_0 0xA8E8 428198350Sedwin#define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4 429198350Sedwin#define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR 43019872Swollman#define L2D_PATTERN_FG_COLOR_RED 0xA8F5 431198350Sedwin#define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6 432198350Sedwin#define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR 43319872Swollman#define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7 43419872Swollman#define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX 43556487Scharnier#define L2D_PAD_1 0xA8F8 43656487Scharnier#define L2D_COMMAND_SET 0xA900 43719872Swollman#define L2D_PAD_2 0xA904 43819872Swollman#define L2D_END_0_END_1 0xA96C 43919872Swollman#define L2D_END_1 L2D_END_0_END_1 44019872Swollman#define L2D_END_0 0xA96E 44119872Swollman#define L2D_DX 0xA970 44219872Swollman#define L2D_X_START 0xA974 44319872Swollman#define L2D_Y_START 0xA978 44419872Swollman#define L2D_Y_COUNT 0xA97C 44519872Swollman 44619872Swollman#define P2D_ADDRESS 0xACD4 44719872Swollman#define P2D_SOURCE_ADDRESS 0xACD4 44819872Swollman#define P2D_DEST_ADDRESS 0xACD8 44919872Swollman#define P2D_CLIP_LEFT_RIGHT 0xACDC 45019872Swollman#define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT 45119872Swollman#define P2D_CLIP_RIGHT 0xACDE 452179530Sjkim#define P2D_CLIP_TOP_BOTTOM 0xACE0 45319872Swollman#define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM 454179530Sjkim#define P2D_CLIP_TOP 0xACE2 45519872Swollman#define P2D_DEST_SOURCE_PITCH 0xACE4 456179530Sjkim#define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH 45719872Swollman#define P2D_DEST_PITCH 0xACE6 458179530Sjkim#define P2D_MONO_PATTERN 0xACE8 45919872Swollman#define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0 46019872Swollman#define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR 46119872Swollman#define P2D_PATTERN_BG_COLOR_RED 0xACF1 46219872Swollman#define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2 46319872Swollman#define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR 46419872Swollman#define P2D_PATTERN_BG_COLOR_INDEX 0xACF3 46519872Swollman#define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX 46619872Swollman#define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4 46719872Swollman#define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR 468179530Sjkim#define P2D_PATTERN_FG_COLOR_RED 0xACF5 469179530Sjkim#define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6 47019872Swollman#define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR 47119872Swollman#define P2D_PATTERN_FG_COLOR_INDEX 0xACF7 47219872Swollman#define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX 47319872Swollman#define P2D_PAD_1 0xACF8 47419872Swollman#define P2D_COMMAND_SET 0xAD00 475179530Sjkim#define P2D_PAD_2 0xAD04 476179530Sjkim#define P2D_RIGHT_DX 0xAD68 47719872Swollman#define P2D_RIGHT_X_START 0xAD6C 478179530Sjkim#define P2D_LEFT_DX 0xAD70 479281733Seadler#define P2D_LEFT_X_START 0xAD74 480179530Sjkim#define P2D_Y_START 0xAD78 48119872Swollman#define P2D_Y_COUNT 0xAD7C 482198350Sedwin 48319872Swollman#define CMD_NOP (7 << 27) /* %1111 << 27 */ 484209190Semaste#define CMD_LINE (3 << 27) /* %0011 << 27 */ 48519872Swollman#define CMD_RECT (4 << 27) /* %0010 << 27 */ 48619872Swollman#define CMD_POLYGON (5 << 27) /* %0101 << 27 */ 487298033Saraujo#define CMD_BITBLT (0 << 27) /* %0000 << 27 */ 48819872Swollman 48919872Swollman#define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */ 490198350Sedwin#define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */ 49119872Swollman#define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */ 49219872Swollman 49319872Swollman#define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */ 49419872Swollman#define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */ 49519872Swollman#define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */ 49619872Swollman 497198350Sedwin#define CMD_CHUNKY (0 << 2) /* %00 << 2 */ 498198350Sedwin#define CMD_HI_COLOR (1 << 2) /* %01 << 2 */ 499281733Seadler#define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */ 50019872Swollman 50119872Swollman#define ROP_FALSE 0x00 502298033Saraujo#define ROP_NOR 0x10 503198350Sedwin#define ROP_ONLYDST 0x20 504179530Sjkim#define ROP_NOTSRC 0x30 50519872Swollman#define ROP_ONLYSRC 0x40 50619872Swollman#define ROP_NOTDST 0x50 50719872Swollman#define ROP_EOR 0x60 50819872Swollman#define ROP_NAND 0x70 509198350Sedwin#define ROP_AND 0x80 510179530Sjkim#define ROP_NEOR 0x90 51119872Swollman#define ROP_DST 0xA0 512179530Sjkim#define ROP_NOTONLYSRC 0xB0 51319872Swollman#define ROP_SRC 0xC0 51419872Swollman#define ROP_NOTONLYDST 0xD0 51519872Swollman#define ROP_OR 0xE0 51619872Swollman#define ROP_TRUE 0xF0 51719872Swollman 51819872Swollman/* Pass-through */ 51919872Swollman#if 0 /* XXX */ 52019872Swollman#define PASS_ADDRESS 0x 52119872Swollman#define PASS_ADDRESS_W 0x 522179530Sjkim#endif 523179530Sjkim 52419872Swollman/* Video DAC */ 525179530Sjkim#define VDAC_ADDRESS 0x03C8 526179530Sjkim#define VDAC_ADDRESS_W 0x03C8 52719872Swollman#define VDAC_ADDRESS_R 0x03C7 52819872Swollman#define VDAC_STATE 0x03C7 52919872Swollman#define VDAC_DATA 0x03C9 53019872Swollman#define VDAC_MASK 0x03C6 53119872Swollman 53219872Swollman 53319872Swollman#define WGfx(ba, idx, val) \ 53419872Swollman do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 53519872Swollman 53619872Swollman#define WSeq(ba, idx, val) \ 53719872Swollman do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 53819872Swollman 53919872Swollman#define WCrt(ba, idx, val) \ 54070486Sben do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 54119872Swollman 54270486Sben#define WAttr(ba, idx, val) \ 543179530Sjkim do { \ 544179530Sjkim unsigned char tmp;\ 54519872Swollman tmp = vgar(ba, ACT_ADDRESS_RESET);\ 54619872Swollman __USE(tmp);\ 54719872Swollman vgaw(ba, ACT_ADDRESS_W, idx);\ 54819872Swollman vgaw(ba, ACT_ADDRESS_W, val);\ 54919872Swollman } while (0) 55019872Swollman 55119872Swollman 55219872Swollman#define SetTextPlane(ba, m) \ 553179530Sjkim do { \ 554179530Sjkim WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 555179530Sjkim WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 55619872Swollman } while (0) 557179530Sjkim 55819872Swollman 55919872Swollman/* Gfx engine busy wait */ 560179530Sjkim 561179530Sjkimstatic inline void 562298033SaraujoGfxBusyWait (volatile void *ba) 56356487Scharnier{ 56419872Swollman int test; 565179530Sjkim 566179530Sjkim do { 567179530Sjkim test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 568179530Sjkim __asm volatile ("nop"); 56919872Swollman } while (!(test & (1 << 13))); 57019872Swollman} 57119872Swollman 57219872Swollman 57319872Swollmanstatic inline void 57419872SwollmanGfxFifoWait(volatile void *ba) 57519872Swollman{ 57619872Swollman#if 0 /* XXX */ 57719872Swollman int test; 57819872Swollman 57919872Swollman do { 58019872Swollman test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 581179530Sjkim } while (test & 0x0f); 582179530Sjkim#endif 58319872Swollman} 58419872Swollman 58519872Swollman 58619872Swollman/* Special wakeup/passthrough registers on graphics boards 587179530Sjkim * 58819872Swollman * The methods have diverged a bit for each board, so 58956487Scharnier * WPass(P) has been converted into a set of specific 59019872Swollman * inline functions. 59170486Sben */ 59219872Swollman 59319872Swollmanstatic inline unsigned char 594179530SjkimRAttr(volatile void *ba, short idx) 595179530Sjkim{ 59619872Swollman 59719872Swollman vgaw(ba, ACT_ADDRESS_W, idx); 59819872Swollman delay(0); 59919872Swollman return vgar(ba, ACT_ADDRESS_R); 60070486Sben} 601179530Sjkim 602179530Sjkimstatic inline unsigned char 60319872SwollmanRSeq(volatile void *ba, short idx) 60419872Swollman{ 60519872Swollman vgaw(ba, SEQ_ADDRESS, idx); 60619872Swollman return vgar(ba, SEQ_ADDRESS_R); 60719872Swollman} 608179530Sjkim 60919872Swollmanstatic inline unsigned char 61019872SwollmanRCrt(volatile void *ba, short idx) 61119872Swollman{ 61219872Swollman vgaw(ba, CRT_ADDRESS, idx); 61319872Swollman return vgar(ba, CRT_ADDRESS_R); 61419872Swollman} 61519872Swollman 61619872Swollmanstatic inline unsigned char 61719872SwollmanRGfx(volatile void *ba, short idx) 61819872Swollman{ 61919872Swollman vgaw(ba, GCT_ADDRESS, idx); 62019872Swollman return vgar(ba, GCT_ADDRESS_R); 621179530Sjkim} 622179530Sjkim 623179530Sjkim#endif /* _GRF_CV3DREG_H */ 624179530Sjkim