tsreg.h revision 1.8
1/* $NetBSD: tsreg.h,v 1.8 2020/09/23 00:46:17 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34/* 35 * 21272 Core Logic registers and constants. 36 */ 37 38#define tsreg() { Generate ctags(1) key. } 39 40/* 41 * Superpage pointer from physical address. 42 */ 43#define S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys)) 44 45/* 46 * {LD,ST}QP: LoaD and STore Quad Physical 47 */ 48#define LDQP(a) (*(volatile long *)ALPHA_PHYS_TO_K0SEG(a)) 49#define STQP(a) LDQP(a) 50 51/* 52 * Define extraction functions for bit fields via length and left,right bitno 53 */ 54#define TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len)))) 55#define TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1) 56 57/* 58 * EV6 has a new superpage which can pass through 44 address bits. (Umm, a 59 * superduperpage?) But, the firmware doesn't turn it on, so we use the old 60 * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes 61 * the needed I/O space access. This is just as well; it means we don't have 62 * to worry about which GENERIC code might get called on other CPU models. 63 * 64 * E.g., we want this: 0x0801##a000##0000 65 * We use this: 0x0101##a000##0000 66 * ...mix in the old SP: 0xffff##fc00##0000##0000 67 * ...after PA sign ext: 0xffff##ff00##a000##0000 68 * (PA<42:41> ignored) 69 */ 70 71/* 72 * This hack allows us to map the I/O address space without using 73 * the KSEG sign extension hack. 74 */ 75#define TS_PHYSADDR(x) \ 76 (((x) & ~0x0100##0000##0000) | 0x0800##0000##0000) 77 78/* 79 * Cchip CSR Map 80 */ 81 82#define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */ 83 84# define CSC_P1P (1L << 14) 85# define CSC_BC(r) TSFIELD((r), 0, 2) 86# define CSC_AW (1L << 8) 87 88#define TS_C_MTR 0x101##a000##0040UL 89 90#define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */ 91 92# define MISC_NXM(r) TSFIELD((r), 28, 1) 93# define MISC_NXM_SRC(r) TSFIELD((r), 29, 3) 94# define MISC_REV(r) TSFIELD((r), 39, 8) 95 96#define TS_C_MPD 0x101##a000##00c0UL 97 98# define MPD_DR 0x08 /* RO: Data receive */ 99# define MPD_CKR 0x04 /* RO: Clock receive */ 100# define MPD_DS 0x02 /* WO: Data send - Must be a 1 to receive */ 101# define MPD_CKS 0x01 /* WO: Clock send */ 102 103#define TS_C_AAR0 0x101##a000##0100UL 104#define TS_C_AAR1 0x101##a000##0140UL 105#define TS_C_AAR2 0x101##a000##0180UL 106#define TS_C_AAR3 0x101##a000##01c0UL 107 108# define AAR_ASIZ(r) TSFIELD((r), 12, 4) 109# define AAR_SPLIT (1L << 8) 110 111#define TS_C_DIM0 0x101##a000##0200UL 112#define TS_C_DIM1 0x101##a000##0240UL 113#define TS_C_DIR0 0x101##a000##0280UL 114#define TS_C_DIR1 0x101##a000##02c0UL 115#define TS_C_DRIR 0x101##a000##0300UL 116#define TS_C_PRBEN 0x101##a000##0340UL 117#define TS_C_IIC0 0x101##a000##0380UL 118#define TS_C_IIC1 0x101##a000##03c0UL 119#define TS_C_MPR0 0x101##a000##0400UL 120#define TS_C_MPR1 0x101##a000##0440UL 121#define TS_C_MPR2 0x101##a000##0480UL 122#define TS_C_MPR3 0x101##a000##04c0UL 123#define TS_C_MCTL 0x101##a000##0500UL 124 125#define TS_C_TTR 0x101##a000##0580UL 126#define TS_C_TDR 0x101##a000##05c0UL 127#define TS_C_DIM2 0x101##a000##0600UL 128#define TS_C_DIM3 0x101##a000##0640UL 129#define TS_C_DIR2 0x101##a000##0680UL 130#define TS_C_DIR3 0x101##a000##06c0UL 131#define TS_C_IIC2 0x101##a000##0700UL 132#define TS_C_IIC3 0x101##a000##0740UL 133 134/* 135 * Dchip CSR Map 136 */ 137 138#define TS_D_DSC 0x101##b000##0800UL 139#define TS_D_STR 0x101##b000##0840UL 140#define TS_D_DREV 0x101##b000##0880UL 141#define TS_D_DSC2 0x101##b000##08c0UL 142 143/* 144 * Pchip CSR Offsets 145 */ 146 147#define P_WSBA0 0x0000 148#define P_WSBA1 0x0040 149#define P_WSBA2 0x0080 150#define P_WSBA3 0x00c0 151 152# define WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20) 153# define WSBA_SG 2 154# define WSBA_ENA 1 155 156#define P_WSM0 0x0100 157#define P_WSM1 0x0140 158#define P_WSM2 0x0180 159#define P_WSM3 0x01c0 160 161# define WSM_AM(r) TSFIELDBB((r), 31, 20) 162# define WSM_LEN(r) ((WSM_AM(r) + 1) << 20) 163 164#define P_TBA0 0x0200 165#define P_TBA1 0x0240 166#define P_TBA2 0x0280 167#define P_TBA3 0x02c0 168 169#define P_PCTL 0x0300 170#define P_PLAT 0x0340 171 /* reserved 0x0380 */ 172#define P_PERROR 0x03c0 173 174# define PER_ERR(r) TSFIELD((r), 0, 12) 175# define PER_ECC(r) TSFIELD((r), 10, 2) 176# define PER_SADR(r) TSFIELD((r), 16, 34) 177# define PER_PADR(r) (TSFIELD((r), 18, 32) << 2) 178# define PER_TRNS(r) TSFIELD((r), 16, 2) 179# define PER_INV(r) TSFIELD((r), 51, 1) 180# define PER_CMD(r) TSFIELD((r), 52, 4) 181# define PER_SYN(r) TSFIELD((r), 56, 8) 182 183#define P_PERRMASK 0x0400 184#define P_PERRSET 0x0440 185#define P_TLBIV 0x0480 186#define P_TLBIA 0x04c0 187 188#define P_PMONCTL 0x0500 189#define P_PMONCNT 0x0540 190 191#define P_SPRST 0x0800 192 193#define TS_STEP 0x40 194 195/* 196 * Pchip I/O offsets 197 */ 198 199#define P_CSRBASE 0x001##8000##0000UL 200#define P_PCI_MEM 0x800##0000##0000UL 201#define P_PCI_IO 0x001##fc00##0000UL 202#define P_PCI_CONFIG 0x001##fe00##0000UL 203 204/* 205 * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1. 206 */ 207 208#define TS_P0(offs) (0x100##0000##0000UL + (offs)) 209#define TS_P1(offs) (0x102##0000##0000UL + (offs)) 210#define TS_Pn(n, offs) (0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs)) 211 212/* 213 * Tsunami Generic Register Type 214 */ 215typedef struct _ts_gr { 216 volatile uint64_t tsg_r; 217 long tsg_deadspace[7]; 218} TS_GR; 219 220/* 221 * Tsunami Pchip 222 */ 223struct ts_pport { 224 TS_GR tsp_resA; 225 TS_GR tsp_error; /* Pchip Error */ 226 227 TS_GR tsp_perrmask; /* Pchip Error Mask */ 228 TS_GR tsp_perrset; /* Pchip Error Set */ 229 TS_GR tsp_tlbiv; /* Translation Buffer Invalidate Virtual */ 230 TS_GR tsp_tlbia; /* Translation Buffer Invalidate All */ 231 232 TS_GR tsp_pmonctl; /* PChip Monitor Control */ 233 TS_GR tsp_pmoncnt; /* PChip Monitor Counters */ 234 TS_GR tsp_resB; 235 TS_GR tsp_resC; 236 237 TS_GR tsp_resD_K[8]; 238}; 239 240struct ts_gport { 241 TS_GR tsp_resA[2]; 242 TS_GR tsp_serror; 243 TS_GR tsp_serrmask; 244 TS_GR tsp_serrset; 245 TS_GR tsp_resB; 246 TS_GR tsp_gperrmask; 247 TS_GR tsp_gperren; 248 TS_GR tsp_gperrset; 249 TS_GR tsp_resC; 250 TS_GR tsp_tlbiv; 251 TS_GR tsp_tlbia; 252 TS_GR tsp_resD[2]; 253 TS_GR tsp_sctl; 254 TS_GR tsp_resE[3]; 255}; 256 257struct ts_aport { 258 TS_GR tsp_resA[2]; 259 TS_GR tsp_agperror; 260 TS_GR tsp_agperrmask; 261 TS_GR tsp_agperrset; 262 TS_GR tsp_agplastwr; 263 TS_GR tsp_aperror; 264 TS_GR tsp_aperrmask; 265 TS_GR tsp_aperrset; 266 TS_GR tsp_resB; 267 TS_GR tsp_tlbiv; 268 TS_GR tsp_tlbia; 269 TS_GR tsp_resC[6]; 270}; 271 272struct ts_pchip { 273 TS_GR tsp_wsba[4]; /* Window Space Base Address */ 274 275 TS_GR tsp_wsm[4]; /* Window Space Mask */ 276 277 TS_GR tsp_tba[4]; /* Translated Base Address */ 278 279 TS_GR tsp_pctl; /* Pchip Control */ 280 TS_GR tsp_plat; /* Pchip Latency */ 281 282 union { 283 struct ts_pport p; 284 struct ts_gport g; 285 struct ts_aport a; 286 } port; 287 288 TS_GR tsp_sprts; /* ??? */ 289 TS_GR tsp_res[31]; 290}; 291