tsc.c revision 1.24 
1/* $NetBSD: tsc.c,v 1.24 2014/02/22 18:42:47 martin Exp $ */
2
3/*-
4 * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by Ross Harvey.
17 * 4. The name of Ross Harvey may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 */
33
34#include "opt_dec_6600.h"
35
36#include <sys/cdefs.h>
37
38__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.24 2014/02/22 18:42:47 martin Exp $");
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/device.h>
43#include <sys/malloc.h>
44
45#include <machine/autoconf.h>
46#include <machine/rpb.h>
47#include <machine/sysarch.h>
48
49#include <dev/isa/isareg.h>
50#include <dev/isa/isavar.h>
51#include <dev/pci/pcireg.h>
52#include <dev/pci/pcivar.h>
53#include <alpha/pci/tsreg.h>
54#include <alpha/pci/tsvar.h>
55
56#include "tsciic.h"
57
58#ifdef DEC_6600
59#include <alpha/pci/pci_6600.h>
60#endif
61
62#define tsc() { Generate ctags(1) key. }
63
64static int tscmatch(device_t, cfdata_t, void *);
65static void tscattach(device_t, device_t, void *);
66
67CFATTACH_DECL_NEW(tsc, 0, tscmatch, tscattach, NULL, NULL);
68
69extern struct cfdriver tsc_cd;
70
71struct tsp_config tsp_configuration[4];
72
73static int tscprint(void *, const char *pnp);
74
75static int tspmatch(device_t, cfdata_t, void *);
76static void tspattach(device_t, device_t, void *);
77
78CFATTACH_DECL_NEW(tsp, 0, tspmatch, tspattach, NULL, NULL);
79
80extern struct cfdriver tsp_cd;
81
82static int tsp_bus_get_window(int, int,
83	struct alpha_bus_space_translation *);
84
85static int tsciicprint(void *, const char *pnp);
86
87static int tsciicmatch(device_t, cfdata_t, void *);
88static void tsciicattach(device_t, device_t, void *);
89
90CFATTACH_DECL_NEW(tsciic, sizeof(struct tsciic_softc), tsciicmatch,
91    tsciicattach, NULL, NULL);
92
93#if NTSCIIC
94extern struct cfdriver tsciic_cd;
95#endif
96
97/* There can be only one */
98static int tscfound;
99
100/* Which hose is the display console connected to? */
101int tsp_console_hose;
102
103static int
104tscmatch(device_t parent, cfdata_t match, void *aux)
105{
106	struct mainbus_attach_args *ma = aux;
107
108	switch (cputype) {
109	case ST_DEC_6600:
110	case ST_DEC_TITAN:
111		return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound;
112	default:
113		return 0;
114	}
115}
116
117static void
118tscattach(device_t parent, device_t self, void * aux)
119{
120	int i;
121	int nbus;
122	uint64_t csc, aar;
123	struct tsp_attach_args tsp;
124	struct tsciic_attach_args tsciic;
125	struct mainbus_attach_args *ma = aux;
126	int titan = cputype == ST_DEC_TITAN;
127
128	tscfound = 1;
129
130	csc = LDQP(TS_C_CSC);
131
132	nbus = 1 + (CSC_BC(csc) >= 2);
133	printf(": 2127%c Core Logic Chipset, Cchip rev %d\n"
134		"%s%d: %c Dchips, %d memory bus%s of %d bytes\n",
135		titan ? '4' : '2', (int)MISC_REV(LDQP(TS_C_MISC)),
136		ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)],
137		nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0));
138	printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot);
139	for (i = 0; i < 4; ++i) {
140		aar = LDQP(TS_C_AAR0 + i * TS_STEP);
141		printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf,
142		    aar & AAR_SPLIT ? " (split)" : "");
143	}
144	printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf);
145
146	memset(&tsp, 0, sizeof tsp);
147	tsp.tsp_name = "tsp";
148	tsp.tsp_slot = 0;
149
150	config_found(self, &tsp, tscprint);
151	if (titan) {
152		tsp.tsp_slot += 2;
153		config_found(self, &tsp, tscprint);
154	}
155
156	if (csc & CSC_P1P) {
157		tsp.tsp_slot = 1;
158		config_found(self, &tsp, tscprint);
159		if (titan) {
160			tsp.tsp_slot += 2;
161			config_found(self, &tsp, tscprint);
162		}
163	}
164
165	memset(&tsciic, 0, sizeof tsciic);
166	tsciic.tsciic_name = "tsciic";
167
168	config_found(self, &tsciic, tsciicprint);
169}
170
171static int
172tscprint(void *aux, const char *p)
173{
174	struct tsp_attach_args *tsp = aux;
175
176	if (p)
177		aprint_normal("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p);
178	return UNCONF;
179}
180
181static int
182tsciicprint(void *aux, const char *p)
183{
184	struct tsciic_attach_args *tsciic = aux;
185
186	if (p)
187		aprint_normal("%s at %s\n", tsciic->tsciic_name, p);
188	else
189		aprint_normal("\n");
190	return UNCONF;
191}
192
193#define tsp() { Generate ctags(1) key. }
194
195static int
196tspmatch(device_t parent, cfdata_t match, void *aux)
197{
198	struct tsp_attach_args *t = aux;
199
200	switch (cputype) {
201	case ST_DEC_6600:
202	case ST_DEC_TITAN:
203		return strcmp(t->tsp_name, tsp_cd.cd_name) == 0;
204	default:
205		return 0;
206	}
207}
208
209static void
210tspattach(device_t parent, device_t self, void *aux)
211{
212	struct pcibus_attach_args pba;
213	struct tsp_attach_args *t = aux;
214	struct tsp_config *pcp;
215
216	printf("\n");
217	pcp = tsp_init(1, t->tsp_slot);
218
219	tsp_dma_init(pcp);
220
221	/*
222	 * Do PCI memory initialization that needs to be deferred until
223	 * malloc is safe.  On the Tsunami, we need to do this after
224	 * DMA is initialized, as well.
225	 */
226	tsp_bus_mem_init2(&pcp->pc_memt, pcp);
227
228	pci_6600_pickintr(pcp);
229
230	pba.pba_iot = &pcp->pc_iot;
231	pba.pba_memt = &pcp->pc_memt;
232	pba.pba_dmat =
233	    alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI);
234	pba.pba_dmat64 = NULL;
235	pba.pba_pc = &pcp->pc_pc;
236	pba.pba_bus = 0;
237	pba.pba_bridgetag = NULL;
238	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
239	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
240	config_found_ia(self, "pcibus", &pba, pcibusprint);
241}
242
243struct tsp_config *
244tsp_init(int mallocsafe, int n)
245	/* n:	 Pchip number */
246{
247	struct tsp_config *pcp;
248	int titan = cputype == ST_DEC_TITAN;
249
250	KASSERT(n >= 0 && n < __arraycount(tsp_configuration));
251	pcp = &tsp_configuration[n];
252	pcp->pc_pslot = n;
253	pcp->pc_iobase = TS_Pn(n, 0);
254	pcp->pc_csr = S_PAGE(TS_Pn(n & 1, P_CSRBASE));
255	if (n & 2) {
256		/* `A' port of PA Chip */
257		pcp->pc_csr++;
258	}
259	if (titan) {
260		/* same address on G and A ports */
261		pcp->pc_tlbia = &pcp->pc_csr->port.g.tsp_tlbia.tsg_r;
262	} else {
263		pcp->pc_tlbia = &pcp->pc_csr->port.p.tsp_tlbia.tsg_r;
264	}
265
266	if (!pcp->pc_initted) {
267		tsp_bus_io_init(&pcp->pc_iot, pcp);
268		tsp_bus_mem_init(&pcp->pc_memt, pcp);
269
270		alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
271		alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
272
273		alpha_bus_get_window = tsp_bus_get_window;
274	}
275	pcp->pc_mallocsafe = mallocsafe;
276	tsp_pci_init(&pcp->pc_pc, pcp);
277	pcp->pc_initted = 1;
278	return pcp;
279}
280
281static int
282tsp_bus_get_window(int type, int window,
283    struct alpha_bus_space_translation *abst)
284{
285	struct tsp_config *tsp = &tsp_configuration[tsp_console_hose];
286	bus_space_tag_t st;
287	int error;
288
289	switch (type) {
290	case ALPHA_BUS_TYPE_PCI_IO:
291		st = &tsp->pc_iot;
292		break;
293
294	case ALPHA_BUS_TYPE_PCI_MEM:
295		st = &tsp->pc_memt;
296		break;
297
298	default:
299		panic("tsp_bus_get_window");
300	}
301
302	error = alpha_bus_space_get_window(st, window, abst);
303	if (error)
304		return error;
305
306	abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start);
307	abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end);
308
309	return 0;
310}
311
312#define tsciic() { Generate ctags(1) key. }
313
314static int
315tsciicmatch(device_t parent, cfdata_t match, void *aux)
316{
317#if NTSCIIC
318	struct tsciic_attach_args *t = aux;
319#endif
320
321	switch (cputype) {
322	case ST_DEC_6600:
323	case ST_DEC_TITAN:
324#if NTSCIIC
325		return strcmp(t->tsciic_name, tsciic_cd.cd_name) == 0;
326#endif
327	default:
328		return 0;
329	}
330}
331
332static void
333tsciicattach(device_t parent, device_t self, void *aux)
334{
335#if NTSCIIC
336	tsciic_init(self);
337#endif
338}
339
340void
341tsc_print_dir(unsigned int indent, unsigned long dir)
342{
343	char buf[60];
344
345	snprintb(buf, 60,
346		 "\177\20"
347		 "b\77Internal Cchip asynchronous error\0"
348		 "b\76Pchip 0 error\0"
349		 "b\75Pchip 1 error\0"
350		 "b\74Pchip 2 error\0"
351		 "b\73Pchip 3 error\0",
352		 dir);
353	IPRINTF(indent, "DIR = %s\n", buf);
354}
355
356void
357tsc_print_misc(unsigned int indent, unsigned long misc)
358{
359	unsigned long tmp = MISC_NXM_SRC(misc);
360
361	if (!MISC_NXM(misc))
362		return;
363
364	IPRINTF(indent, "NXM address detected\n");
365	IPRINTF(indent, "NXM source         = %s %lu\n",
366		tmp <= 3 ? "CPU" : "Pchip", tmp <= 3 ? tmp : tmp - 4);
367}
368