pmap.h revision 1.34
1/* $NetBSD: pmap.h,v 1.34 2000/05/23 05:12:56 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center and by Chris G. Demetriou. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1987 Carnegie-Mellon University 42 * Copyright (c) 1991, 1993 43 * The Regents of the University of California. All rights reserved. 44 * 45 * This code is derived from software contributed to Berkeley by 46 * the Systems Programming Group of the University of Utah Computer 47 * Science Department. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 3. All advertising materials mentioning features or use of this software 58 * must display the following acknowledgement: 59 * This product includes software developed by the University of 60 * California, Berkeley and its contributors. 61 * 4. Neither the name of the University nor the names of its contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 75 * SUCH DAMAGE. 76 * 77 * @(#)pmap.h 8.1 (Berkeley) 6/10/93 78 */ 79 80#ifndef _PMAP_MACHINE_ 81#define _PMAP_MACHINE_ 82 83#if defined(_KERNEL) && !defined(_LKM) 84#include "opt_multiprocessor.h" 85#endif 86 87#include <sys/lock.h> 88#include <sys/queue.h> 89 90#include <machine/pte.h> 91 92/* 93 * Machine-dependent virtual memory state. 94 * 95 * If we ever support processor numbers higher than 63, we'll have to 96 * rethink the CPU mask. 97 * 98 * Note pm_asn and pm_asngen are arrays allocated in pmap_create(). 99 * Their size is based on the PCS count from the HWRPB, and indexed 100 * by processor ID (from `whami'). 101 * 102 * The kernel pmap is a special case; it gets statically-allocated 103 * arrays which hold enough for ALPHA_MAXPROCS. 104 */ 105struct pmap { 106 TAILQ_ENTRY(pmap) pm_list; /* list of all pmaps */ 107 pt_entry_t *pm_lev1map; /* level 1 map */ 108 int pm_count; /* pmap reference count */ 109 struct simplelock pm_slock; /* lock on pmap */ 110 struct pmap_statistics pm_stats; /* pmap statistics */ 111 long pm_nlev2; /* level 2 pt page count */ 112 long pm_nlev3; /* level 3 pt page count */ 113 unsigned int *pm_asn; /* address space number */ 114 unsigned long *pm_asngen; /* ASN generation number */ 115 unsigned long pm_cpus; /* mask of CPUs using pmap */ 116 unsigned long pm_needisync; /* mask of CPUs needing isync */ 117}; 118 119typedef struct pmap *pmap_t; 120 121#define PMAP_ASN_RESERVED 0 /* reserved for Lev1map users */ 122 123extern struct pmap kernel_pmap_store; 124 125#define pmap_kernel() (&kernel_pmap_store) 126 127/* 128 * For each vm_page_t, there is a list of all currently valid virtual 129 * mappings of that page. An entry is a pv_entry_t, the list is pv_table. 130 */ 131typedef struct pv_entry { 132 LIST_ENTRY(pv_entry) pv_list; /* pv_entry list */ 133 struct pmap *pv_pmap; /* pmap where mapping lies */ 134 vaddr_t pv_va; /* virtual address for mapping */ 135 pt_entry_t *pv_pte; /* PTE that maps the VA */ 136} *pv_entry_t; 137 138/* 139 * The head of the list of pv_entry_t's, also contains page attributes. 140 */ 141struct pv_head { 142 LIST_HEAD(, pv_entry) pvh_list; /* pv_entry list */ 143 struct simplelock pvh_slock; /* lock on this head */ 144 int pvh_attrs; /* page attributes */ 145 int pvh_usage; /* page usage */ 146 int pvh_refcnt; /* special use ref count */ 147}; 148 149/* pvh_attrs */ 150#define PGA_MODIFIED 0x01 /* modified */ 151#define PGA_REFERENCED 0x02 /* referenced */ 152 153/* pvh_usage */ 154#define PGU_NORMAL 0 /* free or normal use */ 155#define PGU_PVENT 1 /* PV entries */ 156#define PGU_L1PT 2 /* level 1 page table */ 157#define PGU_L2PT 3 /* level 2 page table */ 158#define PGU_L3PT 4 /* level 3 page table */ 159 160#define PGU_ISPTPAGE(pgu) ((pgu) >= PGU_L1PT) 161 162#define PGU_STRINGS \ 163{ \ 164 "normal", \ 165 "pvent", \ 166 "l1pt", \ 167 "l2pt", \ 168 "l3pt", \ 169} 170 171#ifdef _KERNEL 172 173#ifndef _LKM 174#include "opt_new_scc_driver.h" 175#include "opt_dec_3000_300.h" /* XXX */ 176#include "opt_dec_3000_500.h" /* XXX */ 177#include "opt_dec_kn8ae.h" /* XXX */ 178 179#if defined(NEW_SCC_DRIVER) 180#if defined(DEC_KN8AE) 181#define _PMAP_MAY_USE_PROM_CONSOLE 182#endif 183#else /* ! NEW_SCC_DRIVER */ 184#if defined(DEC_3000_300) \ 185 || defined(DEC_3000_500) \ 186 || defined(DEC_KN8AE) /* XXX */ 187#define _PMAP_MAY_USE_PROM_CONSOLE /* XXX */ 188#endif /* XXX */ 189#endif /* NEW_SCC_DRIVER */ 190 191#if defined(MULTIPROCESSOR) 192void pmap_tlb_shootdown __P((pmap_t, vaddr_t, pt_entry_t)); 193void pmap_do_tlb_shootdown __P((void)); 194#endif /* MULTIPROCESSOR */ 195#endif /* _LKM */ 196 197#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 198#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 199 200extern pt_entry_t *VPT; /* Virtual Page Table */ 201 202#define PMAP_STEAL_MEMORY /* enable pmap_steal_memory() */ 203 204/* 205 * Alternate mapping hooks for pool pages. Avoids thrashing the TLB. 206 */ 207#define PMAP_MAP_POOLPAGE(pa) ALPHA_PHYS_TO_K0SEG((pa)) 208#define PMAP_UNMAP_POOLPAGE(va) ALPHA_K0SEG_TO_PHYS((va)) 209 210paddr_t vtophys __P((vaddr_t)); 211 212/* Machine-specific functions. */ 213void pmap_bootstrap __P((paddr_t ptaddr, u_int maxasn, u_long ncpuids)); 214void pmap_emulate_reference __P((struct proc *p, vaddr_t v, 215 int user, int write)); 216#ifdef _PMAP_MAY_USE_PROM_CONSOLE 217int pmap_uses_prom_console __P((void)); 218#endif 219 220#define pmap_pte_pa(pte) (PG_PFNUM(*(pte)) << PGSHIFT) 221#define pmap_pte_prot(pte) (*(pte) & PG_PROT) 222#define pmap_pte_w(pte) (*(pte) & PG_WIRED) 223#define pmap_pte_v(pte) (*(pte) & PG_V) 224#define pmap_pte_pv(pte) (*(pte) & PG_PVLIST) 225#define pmap_pte_asm(pte) (*(pte) & PG_ASM) 226#define pmap_pte_exec(pte) (*(pte) & PG_EXEC) 227 228#define pmap_pte_set_w(pte, v) \ 229do { \ 230 if (v) \ 231 *(pte) |= PG_WIRED; \ 232 else \ 233 *(pte) &= ~PG_WIRED; \ 234} while (0) 235 236#define pmap_pte_w_chg(pte, nw) ((nw) ^ pmap_pte_w(pte)) 237 238#define pmap_pte_set_prot(pte, np) \ 239do { \ 240 *(pte) &= ~PG_PROT; \ 241 *(pte) |= (np); \ 242} while (0) 243 244#define pmap_pte_prot_chg(pte, np) ((np) ^ pmap_pte_prot(pte)) 245 246static __inline pt_entry_t *pmap_l2pte __P((pmap_t, vaddr_t, pt_entry_t *)); 247static __inline pt_entry_t *pmap_l3pte __P((pmap_t, vaddr_t, pt_entry_t *)); 248 249#define pmap_l1pte(pmap, v) \ 250 (&(pmap)->pm_lev1map[l1pte_index((vaddr_t)(v))]) 251 252static __inline pt_entry_t * 253pmap_l2pte(pmap, v, l1pte) 254 pmap_t pmap; 255 vaddr_t v; 256 pt_entry_t *l1pte; 257{ 258 pt_entry_t *lev2map; 259 260 if (l1pte == NULL) { 261 l1pte = pmap_l1pte(pmap, v); 262 if (pmap_pte_v(l1pte) == 0) 263 return (NULL); 264 } 265 266 lev2map = (pt_entry_t *)ALPHA_PHYS_TO_K0SEG(pmap_pte_pa(l1pte)); 267 return (&lev2map[l2pte_index(v)]); 268} 269 270static __inline pt_entry_t * 271pmap_l3pte(pmap, v, l2pte) 272 pmap_t pmap; 273 vaddr_t v; 274 pt_entry_t *l2pte; 275{ 276 pt_entry_t *l1pte, *lev2map, *lev3map; 277 278 if (l2pte == NULL) { 279 l1pte = pmap_l1pte(pmap, v); 280 if (pmap_pte_v(l1pte) == 0) 281 return (NULL); 282 283 lev2map = (pt_entry_t *)ALPHA_PHYS_TO_K0SEG(pmap_pte_pa(l1pte)); 284 l2pte = &lev2map[l2pte_index(v)]; 285 if (pmap_pte_v(l2pte) == 0) 286 return (NULL); 287 } 288 289 lev3map = (pt_entry_t *)ALPHA_PHYS_TO_K0SEG(pmap_pte_pa(l2pte)); 290 return (&lev3map[l3pte_index(v)]); 291} 292 293/* 294 * Macros for locking pmap structures. 295 * 296 * Note that we if we access the kernel pmap in interrupt context, it 297 * is only to update statistics. Since stats are updated using atomic 298 * operations, locking the kernel pmap is not necessary. Therefore, 299 * it is not necessary to block interrupts when locking pmap strucutres. 300 */ 301#define PMAP_LOCK(pmap) simple_lock(&(pmap)->pm_slock) 302#define PMAP_UNLOCK(pmap) simple_unlock(&(pmap)->pm_slock) 303 304/* 305 * Macro for processing deferred I-stream synchronization. 306 * 307 * The pmap module may defer syncing the user I-stream until the 308 * return to userspace, since the IMB PALcode op can be quite 309 * expensive. Since user instructions won't be executed until 310 * the return to userspace, this can be deferred until userret(). 311 */ 312#define PMAP_USERRET(pmap) \ 313do { \ 314 u_long cpu_mask = (1UL << cpu_number()); \ 315 \ 316 if ((pmap)->pm_needisync & cpu_mask) { \ 317 atomic_clearbits_ulong(&(pmap)->pm_needisync, \ 318 cpu_mask); \ 319 alpha_pal_imb(); \ 320 } \ 321} while (0) 322 323#endif /* _KERNEL */ 324 325#endif /* _PMAP_MACHINE_ */ 326