1258945Sroberto# sh testcase for ldrc, strc 2258945Sroberto# mach: shdsp 3258945Sroberto# as(shdsp): -defsym sim_cpu=1 -dsp 4280849Scy 5280849Scy .include "testutils.inc" 6280849Scy 7280849Scy start 8280849Scy 9280849Scysetrc_imm: 10280849Scy set_grs_a5a5 11280849Scy # Test setrc 12280849Scy # 13280849Scy ldrs lstart 14280849Scy ldre lend 15280849Scy setrc #0xff 16280849Scy get_sr r1 17280849Scy shlr16 r1 18258945Sroberto set_greg 0xfff, r0 19258945Sroberto and r0, r1 20258945Sroberto assertreg 0xff, r1 21258945Sroberto 22258945Sroberto stc rs, r0 ! rs unchanged 23258945Sroberto assertreg0 lstart 24258945Sroberto stc re, r0 ! re unchanged 25258945Sroberto assertreg0 lend 26258945Sroberto 27258945Sroberto set_greg 0xa5a5a5a5, r0 28258945Sroberto set_greg 0xa5a5a5a5, r1 29258945Sroberto 30258945Sroberto test_grs_a5a5 31258945Sroberto 32258945Srobertosetrc_reg: 33258945Sroberto set_grs_a5a5 34280849Scy # Test setrc 35258945Sroberto # 36258945Sroberto ldrs lstart 37258945Sroberto ldre lend 38258945Sroberto set_greg 0xfff, r0 39258945Sroberto setrc r0 40258945Sroberto get_sr r1 41280849Scy shlr16 r1 42258945Sroberto set_greg 0xfff, r0 43258945Sroberto and r0, r1 44258945Sroberto assertreg 0xfff, r1 45258945Sroberto 46280849Scy stc rs, r0 ! rs unchanged 47258945Sroberto assertreg0 lstart 48258945Sroberto stc re, r0 ! re unchanged 49285612Sdelphij assertreg0 lend 50258945Sroberto 51258945Sroberto set_greg 0xa5a5a5a5, r0 52258945Sroberto set_greg 0xa5a5a5a5, r1 53258945Sroberto 54280849Scy test_grs_a5a5 55258945Sroberto 56258945Sroberto bra ldrc_imm 57285612Sdelphij 58258945Sroberto .global lstart 59258945Sroberto .align 2 60258945Srobertolstart: nop 61258945Sroberto nop 62280849Scy nop 63258945Sroberto nop 64258945Sroberto .global lend 65258945Sroberto .align 2 66258945Srobertolend: nop 67258945Sroberto nop 68258945Sroberto nop 69280849Scy nop 70258945Sroberto 71280849Scyldrc_imm: 72258945Sroberto set_grs_a5a5 73258945Sroberto # Test ldrc 74258945Sroberto setrc #0x0 ! zero rc 75258945Sroberto ldrc #0xa5 76280849Scy get_sr r1 77258945Sroberto shlr16 r1 78280849Scy set_greg 0xfff, r0 79258945Sroberto and r0, r1 80258945Sroberto assertreg 0xa5, r1 81258945Sroberto stc rs, r0 ! rs unchanged 82258945Sroberto assertreg0 lstart 83258945Sroberto stc re, r0 84258945Sroberto assertreg0 lend+1 ! bit 0 set in re 85258945Sroberto 86258945Sroberto # fix up re for next test 87258945Sroberto dt r0 ! Ugh! No DEC insn! 88258945Sroberto ldc r0, re 89258945Sroberto 90258945Sroberto set_greg 0xa5a5a5a5, r0 91258945Sroberto set_greg 0xa5a5a5a5, r1 92258945Sroberto 93258945Sroberto test_grs_a5a5 94258945Sroberto 95258945Srobertoldrc_reg: 96258945Sroberto set_grs_a5a5 97258945Sroberto # Test ldrc 98258945Sroberto setrc #0x0 ! zero rc 99258945Sroberto set_greg 0xa5a, r0 100258945Sroberto ldrc r0 101258945Sroberto get_sr r1 102280849Scy shlr16 r1 103258945Sroberto set_greg 0xfff, r0 104258945Sroberto and r0, r1 105258945Sroberto assertreg 0xa5a, r1 106258945Sroberto stc rs, r0 ! rs unchanged 107258945Sroberto assertreg0 lstart 108258945Sroberto stc re, r0 109258945Sroberto assertreg0 lend+1 ! bit 0 set in re 110258945Sroberto 111258945Sroberto set_greg 0xa5a5a5a5, r0 112258945Sroberto set_greg 0xa5a5a5a5, r1 113258945Sroberto 114258945Sroberto test_grs_a5a5 115258945Sroberto 116258945Sroberto pass 117258945Sroberto exit 0 118258945Sroberto 119258945Sroberto