addb.s revision 1.1.1.1
1# Hitachi H8 testcase 'add.b' 2# mach(): all 3# as(h8300): --defsym sim_cpu=0 4# as(h8300h): --defsym sim_cpu=1 5# as(h8300s): --defsym sim_cpu=2 6# as(h8sx): --defsym sim_cpu=3 7# ld(h8300h): -m h8300helf 8# ld(h8300s): -m h8300self 9# ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 # Instructions tested: 14 # add.b #xx:8, rd ; 8 rd xxxxxxxx 15 # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx 16 # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx 17 # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx 18 # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx 19 # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx 20 # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx 21 # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx 22 # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx 23 # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx 24 # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx 25 # add.b rs, rd ; 0 8 rs rd 26 # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ???? 27 # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs 28 # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs 29 # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs 30 # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs 31 # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16 32 # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32 33 # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ???? 34 # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ???? 35 # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ???? 36 # 37 38 # Coming soon: 39 # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx 40 # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8 41 # ... 42 43.data 44pre_byte: .byte 0 45byte_dest: .byte 0 46post_byte: .byte 0 47 48 start 49 50add_b_imm8_reg: 51 set_grs_a5a5 ; Fill all general regs with a fixed pattern 52 ;; fixme set ccr 53 54 ;; add.b #xx:8,Rd 55 add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst 56 57 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 58 test_h_gr16 0xa5aa r0 ; add result: a5 + 5 59.if (sim_cpu) ; non-zero means h8300h, s, or sx 60 test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 61.endif 62 test_gr_a5a5 1 ; Make sure other general regs not disturbed 63 test_gr_a5a5 2 64 test_gr_a5a5 3 65 test_gr_a5a5 4 66 test_gr_a5a5 5 67 test_gr_a5a5 6 68 test_gr_a5a5 7 69 70.if (sim_cpu == h8sx) 71add_b_imm8_rdind: 72 set_grs_a5a5 ; Fill all general regs with a fixed pattern 73 set_ccr_zero 74 75 ;; add.b #xx:8,@eRd 76 mov #byte_dest, er0 77 add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst 78;;; .word 0x7d00 79;;; .word 0x8005 80 81 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 82 test_ovf_clear 83 test_zero_clear 84 test_neg_clear 85 86 test_h_gr32 byte_dest, er0 ; er0 still contains address 87 test_gr_a5a5 1 ; Make sure other general regs not disturbed 88 test_gr_a5a5 2 89 test_gr_a5a5 3 90 test_gr_a5a5 4 91 test_gr_a5a5 5 92 test_gr_a5a5 6 93 test_gr_a5a5 7 94 95 ;; Now check the result of the add to memory. 96 sub.b r0l, r0l 97 mov.b @byte_dest, r0l 98 cmp.b #5, r0l 99 beq .L1 100 fail 101.L1: 102 103add_b_imm8_rdpostinc: 104 set_grs_a5a5 ; Fill all general regs with a fixed pattern 105 set_ccr_zero 106 107 ;; add.b #xx:8,@eRd+ 108 mov #byte_dest, er0 109 add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst 110;;; .word 0x0174 111;;; .word 0x6c08 112;;; .word 0x8005 113 114 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 115 test_ovf_clear 116 test_zero_clear 117 test_neg_clear 118 119 test_h_gr32 post_byte, er0 ; er0 contains address plus one 120 test_gr_a5a5 1 ; Make sure other general regs not disturbed 121 test_gr_a5a5 2 122 test_gr_a5a5 3 123 test_gr_a5a5 4 124 test_gr_a5a5 5 125 test_gr_a5a5 6 126 test_gr_a5a5 7 127 128 ;; Now check the result of the add to memory. 129 sub.b r0l, r0l 130 mov.b @byte_dest, r0l 131 cmp.b #10, r0l 132 beq .L2 133 fail 134.L2: 135 136add_b_imm8_rdpostdec: 137 set_grs_a5a5 ; Fill all general regs with a fixed pattern 138 set_ccr_zero 139 140 ;; add.b #xx:8,@eRd- 141 mov #byte_dest, er0 142 add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst 143;;; .word 0x0176 144;;; .word 0x6c08 145;;; .word 0x8005 146 147 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 148 test_ovf_clear 149 test_zero_clear 150 test_neg_clear 151 152 test_h_gr32 pre_byte, er0 ; er0 contains address minus one 153 test_gr_a5a5 1 ; Make sure other general regs not disturbed 154 test_gr_a5a5 2 155 test_gr_a5a5 3 156 test_gr_a5a5 4 157 test_gr_a5a5 5 158 test_gr_a5a5 6 159 test_gr_a5a5 7 160 161 ;; Now check the result of the add to memory. 162 sub.b r0l, r0l 163 mov.b @byte_dest, r0l 164 cmp.b #15, r0l 165 beq .L3 166 fail 167.L3: 168 169add_b_imm8_rdpreinc: 170 set_grs_a5a5 ; Fill all general regs with a fixed pattern 171 set_ccr_zero 172 173 ;; add.b #xx:8,@+eRd 174 mov #pre_byte, er0 175 add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst 176;;; .word 0x0175 177;;; .word 0x6c08 178;;; .word 0x8005 179 180 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 181 test_ovf_clear 182 test_zero_clear 183 test_neg_clear 184 185 test_h_gr32 byte_dest, er0 ; er0 contains destination address 186 test_gr_a5a5 1 ; Make sure other general regs not disturbed 187 test_gr_a5a5 2 188 test_gr_a5a5 3 189 test_gr_a5a5 4 190 test_gr_a5a5 5 191 test_gr_a5a5 6 192 test_gr_a5a5 7 193 194 ;; Now check the result of the add to memory. 195 sub.b r0l, r0l 196 mov.b @byte_dest, r0l 197 cmp.b #20, r0l 198 beq .L4 199 fail 200.L4: 201 202add_b_imm8_rdpredec: 203 set_grs_a5a5 ; Fill all general regs with a fixed pattern 204 set_ccr_zero 205 206 ;; add.b #xx:8,@-eRd 207 mov #post_byte, er0 208 add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst 209;;; .word 0x0177 210;;; .word 0x6c08 211;;; .word 0x8005 212 213 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 214 test_ovf_clear 215 test_zero_clear 216 test_neg_clear 217 218 test_h_gr32 byte_dest, er0 ; er0 contains destination address 219 test_gr_a5a5 1 ; Make sure other general regs not disturbed 220 test_gr_a5a5 2 221 test_gr_a5a5 3 222 test_gr_a5a5 4 223 test_gr_a5a5 5 224 test_gr_a5a5 6 225 test_gr_a5a5 7 226 227 ;; Now check the result of the add to memory. 228 sub.b r0l, r0l 229 mov.b @byte_dest, r0l 230 cmp.b #25, r0l 231 beq .L5 232 fail 233.L5: 234 235add_b_imm8_disp16: 236 set_grs_a5a5 ; Fill all general regs with a fixed pattern 237 set_ccr_zero 238 239 ;; add.b #xx:8,@(dd:16, eRd) 240 mov #post_byte, er0 241 add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest. 242;;; .word 0x0174 243;;; .word 0x6e08 244;;; .word 0xffff 245;;; .word 0x8005 246 247 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 248 test_ovf_clear 249 test_zero_clear 250 test_neg_clear 251 252 test_h_gr32 post_byte, er0 ; er0 contains address plus one 253 test_gr_a5a5 1 ; Make sure other general regs not disturbed 254 test_gr_a5a5 2 255 test_gr_a5a5 3 256 test_gr_a5a5 4 257 test_gr_a5a5 5 258 test_gr_a5a5 6 259 test_gr_a5a5 7 260 261 ;; Now check the result of the add to memory. 262 sub.b r0l, r0l 263 mov.b @byte_dest, r0l 264 cmp.b #30, r0l 265 beq .L6 266 fail 267.L6: 268 269add_b_imm8_disp32: 270 set_grs_a5a5 ; Fill all general regs with a fixed pattern 271 set_ccr_zero 272 273 ;; add.b #xx:8,@(dd:32, eRd) 274 mov #pre_byte, er0 275 add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest. 276;;; .word 0x7804 277;;; .word 0x6a28 278;;; .word 0x0000 279;;; .word 0x0001 280;;; .word 0x8005 281 282 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 283 test_ovf_clear 284 test_zero_clear 285 test_neg_clear 286 287 test_h_gr32 pre_byte, er0 ; er0 contains address minus one 288 test_gr_a5a5 1 ; Make sure other general regs not disturbed 289 test_gr_a5a5 2 290 test_gr_a5a5 3 291 test_gr_a5a5 4 292 test_gr_a5a5 5 293 test_gr_a5a5 6 294 test_gr_a5a5 7 295 296 ;; Now check the result of the add to memory. 297 sub.b r0l, r0l 298 mov.b @byte_dest, r0l 299 cmp.b #35, r0l 300 beq .L7 301 fail 302.L7: 303 304add_b_imm8_abs8: 305 set_grs_a5a5 ; Fill all general regs with a fixed pattern 306 set_ccr_zero 307 308 ;; add.b reg8,@aa:8 309 ;; NOTE: for abs8, we will use the SBR register as a base, 310 ;; since otherwise we would have to make sure that the destination 311 ;; was in the zero page. 312 ;; 313 mov #byte_dest-100, er0 314 ldc er0, sbr 315 add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest 316;;; .word 0x7f64 317;;; .word 0x8005 318 319 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 320 test_ovf_clear 321 test_zero_clear 322 test_neg_clear 323 324 test_h_gr32 byte_dest-100, er0 ; reg 0 has base address 325 test_gr_a5a5 1 ; Make sure other general regs not disturbed 326 test_gr_a5a5 2 327 test_gr_a5a5 3 328 test_gr_a5a5 4 329 test_gr_a5a5 5 330 test_gr_a5a5 6 331 test_gr_a5a5 7 332 333 ;; Now check the result of the add to memory. 334 sub.b r0l, r0l 335 mov.b @byte_dest, r0l 336 cmp.b #40, r0l 337 beq .L8 338 fail 339.L8: 340 341add_b_imm8_abs16: 342 set_grs_a5a5 ; Fill all general regs with a fixed pattern 343 set_ccr_zero 344 345 ;; add.b #xx:8,@aa:16 346 add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest 347;;; .word 0x6a18 348;;; .word byte_dest 349;;; .word 0x8005 350 351 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 352 test_ovf_clear 353 test_zero_clear 354 test_neg_clear 355 356 test_gr_a5a5 0 ; Make sure other general regs not disturbed 357 test_gr_a5a5 1 358 test_gr_a5a5 2 359 test_gr_a5a5 3 360 test_gr_a5a5 4 361 test_gr_a5a5 5 362 test_gr_a5a5 6 363 test_gr_a5a5 7 364 365 ;; Now check the result of the add to memory. 366 sub.b r0l, r0l 367 mov.b @byte_dest, r0l 368 cmp.b #45, r0l 369 beq .L9 370 fail 371.L9: 372 373add_b_imm8_abs32: 374 set_grs_a5a5 ; Fill all general regs with a fixed pattern 375 set_ccr_zero 376 377 ;; add.b #xx:8,@aa:32 378 add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest 379;;; .word 0x6a38 380;;; .long byte_dest 381;;; .word 0x8005 382 383 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 384 test_ovf_clear 385 test_zero_clear 386 test_neg_clear 387 388 test_gr_a5a5 0 ; Make sure other general regs not disturbed 389 test_gr_a5a5 1 390 test_gr_a5a5 2 391 test_gr_a5a5 3 392 test_gr_a5a5 4 393 test_gr_a5a5 5 394 test_gr_a5a5 6 395 test_gr_a5a5 7 396 397 ;; Now check the result of the add to memory. 398 sub.b r0l, r0l 399 mov.b @byte_dest, r0l 400 cmp.b #50, r0l 401 beq .L10 402 fail 403.L10: 404 405.endif 406 407add_b_reg8_reg8: 408 set_grs_a5a5 ; Fill all general regs with a fixed pattern 409 ;; fixme set ccr 410 411 ;; add.b Rs,Rd 412 mov.b #5, r0h 413 add.b r0h, r0l ; Register operand 414 415 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 416 test_h_gr16 0x05aa r0 ; add result: a5 + 5 417.if (sim_cpu) ; non-zero means h8300h, s, or sx 418 test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 419.endif 420 test_gr_a5a5 1 ; Make sure other general regs not disturbed 421 test_gr_a5a5 2 422 test_gr_a5a5 3 423 test_gr_a5a5 4 424 test_gr_a5a5 5 425 test_gr_a5a5 6 426 test_gr_a5a5 7 427 428.if (sim_cpu == h8sx) 429add_b_reg8_rdind: 430 set_grs_a5a5 ; Fill all general regs with a fixed pattern 431 set_ccr_zero 432 433 ;; add.b rs8,@eRd ; Add to register indirect 434 mov #byte_dest, er0 435 mov #5, r1l 436 add.b r1l, @er0 ; reg8 src, reg indirect dest 437;;; .word 0x7d00 438;;; .word 0x0890 439 440 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 441 test_ovf_clear 442 test_zero_clear 443 test_neg_clear 444 445 test_h_gr32 byte_dest er0 ; er0 still contains address 446 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 447 448 test_gr_a5a5 2 ; Make sure other general regs not disturbed 449 test_gr_a5a5 3 450 test_gr_a5a5 4 451 test_gr_a5a5 5 452 test_gr_a5a5 6 453 test_gr_a5a5 7 454 455 ;; Now check the result of the add to memory. 456 sub.b r0l, r0l 457 mov.b @byte_dest, r0l 458 cmp.b #55, r0l 459 beq .L11 460 fail 461.L11: 462 463add_b_reg8_rdpostinc: 464 set_grs_a5a5 ; Fill all general regs with a fixed pattern 465 set_ccr_zero 466 467 ;; add.b rs8,@eRd+ ; Add to register post-increment 468 mov #byte_dest, er0 469 mov #5, r1l 470 add.b r1l, @er0+ ; reg8 src, reg post-incr dest 471;;; .word 0x0179 472;;; .word 0x8019 473 474 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 475 test_ovf_clear 476 test_zero_clear 477 test_neg_clear 478 479 test_h_gr32 post_byte er0 ; er0 contains address plus one 480 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 481 482 test_gr_a5a5 2 ; Make sure other general regs not disturbed 483 test_gr_a5a5 3 484 test_gr_a5a5 4 485 test_gr_a5a5 5 486 test_gr_a5a5 6 487 test_gr_a5a5 7 488 489 ;; Now check the result of the add to memory. 490 sub.b r0l, r0l 491 mov.b @byte_dest, r0l 492 cmp.b #60, r0l 493 beq .L12 494 fail 495.L12: 496 ;; special case same register 497 mov.l #byte_dest, er0 498 mov.b @er0, r1h 499 mov.b r0l, r1l 500 add.b r0l, @er0+ 501 inc.b r1l 502 add.b r1h, r1l 503 mov.b @byte_dest, r0l 504 cmp.b r1l, r0l 505 beq .L22 506 fail 507.L22: 508 ;; restore previous value 509 mov.b r1h, @byte_dest 510 511add_b_reg8_rdpostdec: 512 set_grs_a5a5 ; Fill all general regs with a fixed pattern 513 set_ccr_zero 514 515 ;; add.b rs8,@eRd- ; Add to register post-decrement 516 mov #byte_dest, er0 517 mov #5, r1l 518 add.b r1l, @er0- ; reg8 src, reg post-decr dest 519;;; .word 0x0179 520;;; .word 0xa019 521 522 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 523 test_ovf_clear 524 test_zero_clear 525 test_neg_clear 526 527 test_h_gr32 pre_byte er0 ; er0 contains address minus one 528 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 529 530 test_gr_a5a5 2 ; Make sure other general regs not disturbed 531 test_gr_a5a5 3 532 test_gr_a5a5 4 533 test_gr_a5a5 5 534 test_gr_a5a5 6 535 test_gr_a5a5 7 536 537 ;; Now check the result of the add to memory. 538 sub.b r0l, r0l 539 mov.b @byte_dest, r0l 540 cmp.b #65, r0l 541 beq .L13 542 fail 543.L13: 544 ;; special case same register 545 mov.l #byte_dest, er0 546 mov.b @er0, r1h 547 mov.b r0l, r1l 548 add.b r0l, @er0- 549 dec.b r1l 550 add.b r1h, r1l 551 mov.b @byte_dest, r0l 552 cmp.b r1l, r0l 553 beq .L23 554 fail 555.L23: 556 ;; restore previous value 557 mov.b r1h, @byte_dest 558 559add_b_reg8_rdpreinc: 560 set_grs_a5a5 ; Fill all general regs with a fixed pattern 561 set_ccr_zero 562 563 ;; add.b rs8,@+eRd ; Add to register pre-increment 564 mov #pre_byte, er0 565 mov #5, r1l 566 add.b r1l, @+er0 ; reg8 src, reg pre-incr dest 567;;; .word 0x0179 568;;; .word 0x9019 569 570 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 571 test_ovf_clear 572 test_zero_clear 573 test_neg_clear 574 575 test_h_gr32 byte_dest er0 ; er0 contains destination address 576 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 577 578 test_gr_a5a5 2 ; Make sure other general regs not disturbed 579 test_gr_a5a5 3 580 test_gr_a5a5 4 581 test_gr_a5a5 5 582 test_gr_a5a5 6 583 test_gr_a5a5 7 584 585 ;; Now check the result of the add to memory. 586 sub.b r0l, r0l 587 mov.b @byte_dest, r0l 588 cmp.b #70, r0l 589 beq .L14 590 fail 591.L14: 592 ;; special case same register 593 mov.b @byte_dest, r1h 594 mov.l #pre_byte, er0 595 mov.b r0l, r1l 596 add.b r0l, @+er0 597 inc.b r1l 598 add.b r1h, r1l 599 mov.b @byte_dest, r0l 600 cmp.b r1l, r0l 601 beq .L24 602 fail 603.L24: 604 ;; restore previous value 605 mov.b r1h, @byte_dest 606 607add_b_reg8_rdpredec: 608 set_grs_a5a5 ; Fill all general regs with a fixed pattern 609 set_ccr_zero 610 611 ;; add.b rs8,@-eRd ; Add to register pre-decrement 612 mov #post_byte, er0 613 mov #5, r1l 614 add.b r1l, @-er0 ; reg8 src, reg pre-decr dest 615;;; .word 0x0179 616;;; .word 0xb019 617 618 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 619 test_ovf_clear 620 test_zero_clear 621 test_neg_clear 622 623 test_h_gr32 byte_dest er0 ; er0 contains destination address 624 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 625 626 test_gr_a5a5 2 ; Make sure other general regs not disturbed 627 test_gr_a5a5 3 628 test_gr_a5a5 4 629 test_gr_a5a5 5 630 test_gr_a5a5 6 631 test_gr_a5a5 7 632 633 ;; Now check the result of the add to memory. 634 sub.b r0l, r0l 635 mov.b @byte_dest, r0l 636 cmp.b #75, r0l 637 beq .L15 638 fail 639.L15: 640 ;; special case same register 641 mov.l #post_byte, er0 642 mov.b @byte_dest, r1h 643 mov.b r0l, r1l 644 add.b r0l, @-er0 645 dec.b r1l 646 add.b r1h, r1l 647 mov.b @byte_dest, r0l 648 cmp.b r1l, r0l 649 beq .L25 650 fail 651.L25: 652 ;; restore previous value 653 mov.b r1h, @byte_dest 654 655add_b_reg8_disp16: 656 set_grs_a5a5 ; Fill all general regs with a fixed pattern 657 set_ccr_zero 658 659 ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement 660 mov #pre_byte, er0 661 mov #5, r1l 662 add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest 663;;; .word 0x0179 664;;; .word 0xc019 665;;; .word 0x0001 666 667 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 668 test_ovf_clear 669 test_zero_clear 670 test_neg_clear 671 672 test_h_gr32 pre_byte er0 ; er0 contains address minus one 673 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 674 675 test_gr_a5a5 2 ; Make sure other general regs not disturbed 676 test_gr_a5a5 3 677 test_gr_a5a5 4 678 test_gr_a5a5 5 679 test_gr_a5a5 6 680 test_gr_a5a5 7 681 682 ;; Now check the result of the add to memory. 683 sub.b r0l, r0l 684 mov.b @byte_dest, r0l 685 cmp.b #80, r0l 686 beq .L16 687 fail 688.L16: 689 690add_b_reg8_disp32: 691 set_grs_a5a5 ; Fill all general regs with a fixed pattern 692 set_ccr_zero 693 694 ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement 695 mov #post_byte, er0 696 mov #5, r1l 697 add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest 698;;; .word 0x0179 699;;; .word 0xd819 700;;; .word 0xffff 701;;; .word 0xffff 702 703 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 704 test_ovf_clear 705 test_zero_clear 706 test_neg_clear 707 708 test_h_gr32 post_byte er0 ; er0 contains address plus one 709 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load 710 711 test_gr_a5a5 2 ; Make sure other general regs not disturbed 712 test_gr_a5a5 3 713 test_gr_a5a5 4 714 test_gr_a5a5 5 715 test_gr_a5a5 6 716 test_gr_a5a5 7 717 718 ;; Now check the result of the add to memory. 719 sub.b r0l, r0l 720 mov.b @byte_dest, r0l 721 cmp.b #85, r0l 722 beq .L17 723 fail 724.L17: 725 726add_b_reg8_abs8: 727 set_grs_a5a5 ; Fill all general regs with a fixed pattern 728 set_ccr_zero 729 730 ;; add.b reg8,@aa:8 731 ;; NOTE: for abs8, we will use the SBR register as a base, 732 ;; since otherwise we would have to make sure that the destination 733 ;; was in the zero page. 734 ;; 735 mov #byte_dest-100, er0 736 ldc er0, sbr 737 mov #5, r1l 738 add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest 739;;; .word 0x7f64 740;;; .word 0x0890 741 742 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 743 test_ovf_clear 744 test_zero_clear 745 test_neg_clear 746 747 test_h_gr32 byte_dest-100, er0 ; reg 0 has base address 748 test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load 749 test_gr_a5a5 2 ; Make sure other general regs not disturbed 750 test_gr_a5a5 3 751 test_gr_a5a5 4 752 test_gr_a5a5 5 753 test_gr_a5a5 6 754 test_gr_a5a5 7 755 756 ;; Now check the result of the add to memory. 757 sub.b r0l, r0l 758 mov.b @byte_dest, r0l 759 cmp.b #90, r0l 760 beq .L18 761 fail 762.L18: 763 764add_b_reg8_abs16: 765 set_grs_a5a5 ; Fill all general regs with a fixed pattern 766 set_ccr_zero 767 768 ;; add.b reg8,@aa:16 769 mov #5, r0l 770 add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest 771;;; .word 0x6a18 772;;; .word byte_dest 773;;; .word 0x0880 774 775 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 776 test_ovf_clear 777 test_zero_clear 778 test_neg_clear 779 780 test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load 781 test_gr_a5a5 1 ; Make sure other general regs not disturbed 782 test_gr_a5a5 2 783 test_gr_a5a5 3 784 test_gr_a5a5 4 785 test_gr_a5a5 5 786 test_gr_a5a5 6 787 test_gr_a5a5 7 788 789 ;; Now check the result of the add to memory. 790 sub.b r0l, r0l 791 mov.b @byte_dest, r0l 792 cmp.b #95, r0l 793 beq .L19 794 fail 795.L19: 796 797add_b_reg8_abs32: 798 set_grs_a5a5 ; Fill all general regs with a fixed pattern 799 set_ccr_zero 800 801 ;; add.b reg8,@aa:32 802 mov #5, r0l 803 add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest 804;;; .word 0x6a38 805;;; .long byte_dest 806;;; .word 0x0880 807 808 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 809 test_ovf_clear 810 test_zero_clear 811 test_neg_clear 812 813 test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load 814 test_gr_a5a5 1 ; Make sure other general regs not disturbed 815 test_gr_a5a5 2 816 test_gr_a5a5 3 817 test_gr_a5a5 4 818 test_gr_a5a5 5 819 test_gr_a5a5 6 820 test_gr_a5a5 7 821 822 ;; Now check the result of the add to memory. 823 sub.b r0l, r0l 824 mov.b @byte_dest, r0l 825 cmp.b #100, r0l 826 beq .L20 827 fail 828.L20: 829 830.endif 831 832 pass 833 834 exit 0 835