1#mach: crisv10 crisv32 2#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" 3#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" 4#output: /rv: WD\n 5#output: /rv: REG R 0xd0000032\n 6#output: /rv: := 0xabcdef01\n 7#output: /rv: IRQ 0x4\n 8#output: /rv: IRQ 0x8\n 9#output: /rv: REG R 0xd0000036\n 10#output: /rv: := 0x76543210\n 11#output: /rv: REG R 0xd0000030\n 12#output: /rv: IRQ 0x0\n 13#output: /rv: := 0xeeff4455\n 14#output: pass\n 15 16# Much like irq4.ms, but modified to test vector case for multiple-int. 17 18#r W, 19#r r,a8832,abcdef01 20#r I,4 21#r I,8 22#r r,a8836,76543210 23#r I,0 24#r r,a8830,eeff4455 25 26 .lcomm dummy,4 27 28 .include "testutils.inc" 29 start 30 test_h_mem 0xabcdef01 0xd0000032 31 .if ..asm.arch.cris.v32 32 move irqvec1,$ebp 33 .else 34 move irqvec1,$ibr 35 .endif 36 ei 37 test_h_mem 0,dummy 38killme: 39 fail 40 41irq0xae: 42 test_h_mem 0x76543210 0xd0000036 43 test_h_mem 0xeeff4455 0xd0000030 44 pass 45 46 singlevec irqvec1,0xae,irq0xae 47