1# mach: crisv32
2# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n
3
4; Check for protected operations being NOP in user mode, for the
5; parts implemented in this simulator.
6
7 .include "testutils.inc"
8 start
9 move 0,ccs
10 move 0,usp
11 move 0,pid
12 move 0,srs
13 move 0,ebp
14 move 0,spc
15 setf u
16
17; Flag settings, besides what's tested in rfn.ms, rfe.ms and
18; sfe.ms.
19 setf i
20 move ccs,r3
21 dumpr3		; 0x40
22
23 clearf u
24 move ccs,r3
25 dumpr3		; 0x40
26
27 move 0xc0000300,ccs
28 move ccs,r3
29 dumpr3		; 0x140
30
31; R14==USP
32 move.d 0xabadefb0,r14
33 nop
34 nop
35 nop
36 move usp,r3
37 dumpr3		; 0xabadefb0
38 move 0x6543789c,usp
39 nop
40 nop
41 nop
42 move.d r14,r3
43 dumpr3		; 0x6543789c
44
45; We can't go back to kernel mode, so we can't check that R14 in
46; kernel mode wasn't affected.
47
48; Moves to protected special registers.
49 .macro testsr reg,val=-1
50 move \val,\reg
51 ; Registers shorter than dword will not affect the rest of the
52 ; general register when copied using a move insn.
53 clear.d r3
54; Three cycles are needed between move to protected register and
55; read from it, to avoid reading undefined contents due to
56; incomplete forwarding.
57 nop
58 nop
59 move \reg,r3
60 dumpr3
61 moveq \val,r3
62 move r3,\reg
63 clear.d r3
64 nop
65 nop
66 move \reg,r3
67 dumpr3
68 .endm
69
70 testsr pid	; 0 0
71 testsr srs,3	; 0 0
72 testsr ebp	; 0 0
73 testsr spc	; 0 0
74
75 quit
76