1//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp
2// Description: LMU protection exceptions
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(selfcheck.inc)
11include(std.inc)
12include(mmrs.inc)
13
14//-------------------------------------
15
16// Test LMU/CPLB exceptions
17
18// Basic outline:
19//   Set exception handler
20//   program CPLB Entries
21//   Enable CPLB in DMEM_CNTL
22//   perform access
23//   verify exception occurred
24
25CHECK_INIT(p5, 0xEFFFFFFC);
26
27//-------------------------
28// Zero the CPLB Address and Data regs.
29
30	LD32(p0, DCPLB_ADDR0);
31	R0 = 0;
32	[ P0 ++ ] = R0;	// 0
33	[ P0 ++ ] = R0;	// 1
34	[ P0 ++ ] = R0;	// 2
35	[ P0 ++ ] = R0;	// 3
36	[ P0 ++ ] = R0;	// 4
37	[ P0 ++ ] = R0;	// 5
38	[ P0 ++ ] = R0;	// 6
39	[ P0 ++ ] = R0;	// 7
40	[ P0 ++ ] = R0;	// 8
41	[ P0 ++ ] = R0;	// 9
42	[ P0 ++ ] = R0;	// 10
43	[ P0 ++ ] = R0;	// 11
44	[ P0 ++ ] = R0;	// 12
45	[ P0 ++ ] = R0;	// 13
46	[ P0 ++ ] = R0;	// 14
47	[ P0 ++ ] = R0;	// 15
48
49	LD32(p0, DCPLB_DATA0);
50	[ P0 ++ ] = R0;	// 0
51	[ P0 ++ ] = R0;	// 1
52	[ P0 ++ ] = R0;	// 2
53	[ P0 ++ ] = R0;	// 3
54	[ P0 ++ ] = R0;	// 4
55	[ P0 ++ ] = R0;	// 5
56	[ P0 ++ ] = R0;	// 6
57	[ P0 ++ ] = R0;	// 7
58	[ P0 ++ ] = R0;	// 8
59	[ P0 ++ ] = R0;	// 9
60	[ P0 ++ ] = R0;	// 10
61	[ P0 ++ ] = R0;	// 11
62	[ P0 ++ ] = R0;	// 12
63	[ P0 ++ ] = R0;	// 13
64	[ P0 ++ ] = R0;	// 14
65	[ P0 ++ ] = R0;	// 15
66
67	// Now set the CPLB entries we will need
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93	// Data area for the desired error
94	WR_MMR(DCPLB_ADDR0, 0x800, p0, r0);
95	WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0);
96	WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW, p0, r0);
97	WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0);
98	WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0);
99	WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0);
100	WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0);
101	WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0);
102	WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0);
103
104	// CHECKREG segment
105	WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0);
106	WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0);
107
108	//  MMR space
109	WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0);
110	WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0);
111
112	// setup interrupt controller with exception handler address
113	WR_MMR_LABEL(EVT3,  handler, p0, r1);
114	WR_MMR_LABEL(EVT15, int_15, p0, r1);
115	WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
116	WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
117
118	// enable CPLB
119	WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
120	NOP;NOP;NOP;NOP;NOP;	// in lieu of CSYNC
121
122	// go to user mode. and enable exceptions
123	LD32_LABEL(r0, User);
124	RETI = R0;
125
126	// But first raise interrupt 15 so we can do one test
127	// in supervisor mode.
128	RAISE 15;
129	NOP;
130
131	RTI;
132
133	// Nops to work around ICache bug
134	NOP;NOP;NOP;NOP;NOP;
135	NOP;NOP;NOP;NOP;NOP;
136
137
138int_15:
139	// Interrupt 15 handler - needed to try supervisor access with exceptions enabled
140	//-------------------------------------------------------
141	// Protection violation - Illegal Supervisor Write Access
142	R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
143
144	LD32(p1, 0x800);
145	LD32(r1, 0xDEADBEEF);
146
147	LD32(p2, DCPLB_DATA0);
148	LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
149
150	LD32(p3, DCPLB_DATA1);
151	LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
152
153
154X0:	[ P1 ] = R1;		// Exception should occur here
155
156
157	// Now check that handler read correct values
158	CHECKREG(r4,0x23);			// supv and EXCPT_PROT
159	CHECKREG(r5, 0x800);
160	CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0));
161	CHECKREG_SYM(r7, X0, r0);			// RETX should be value of X0	(HARDCODED ADDR!!)
162
163	// go to user mode. and enable exceptions
164	LD32_LABEL(r0, User);
165	RTI;
166	NOP;NOP;NOP;NOP;NOP;
167	NOP;NOP;NOP;NOP;NOP;
168
169
170User:
171	NOP;NOP;NOP;NOP;NOP;
172
173	//-------------------------------------------------------
174	// Protection violation - Illegal User Write Access
175	R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
176
177	LD32(p1, 0x1000);
178	LD32(r1, 0xDEADBEEF);
179
180
181	// values to fix up current test
182	LD32(p2, DCPLB_DATA1);
183	LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
184
185	// values for next test
186	LD32(p3, DCPLB_DATA2);
187	LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE);
188
189X1:	[ P1 ] = R1;		// Exception should occur here
190
191	// Now check that handler read correct values
192
193	CHECKREG(r4,0x23);			// supv and EXCPT_PROT
194	CHECKREG(r5, 0x1000);
195	CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB1));
196	CHECKREG_SYM(r7, X1, r0);			// RETX should be value of X1	(HARDCODED ADDR!!)
197
198
199	//-------------------------------------------------------
200	// Protection violation - Illegal User Read Access
201	R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
202
203	LD32(p1, 0x2000);
204	LD32(r1, 0xDEADBEEF);
205
206	LD32(p2, DCPLB_DATA2);
207	LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR);
208
209	LD32(p3, DCPLB_DATA3);
210	LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
211
212X2:	//[p1] = r1;		// Exception should occur here
213	R0 = [ P1 ];
214
215
216	// Now check that handler read correct values
217	CHECKREG(r4,0x23);			// supv and EXCPT_PROT
218	CHECKREG(r5, 0x2000);
219	CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER | FAULT_CPLB2));
220	CHECKREG_SYM(r7, X2, r0);			// RETX should be value of X2	(HARDCODED ADDR!!)
221
222	//-------------------------------------------------------
223	// Protection violation - Illegal Dirty Page Access
224	R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
225
226	LD32(p1, 0x3000);
227	LD32(r1, 0xDEADBEEF);
228
229	LD32(p2, DCPLB_DATA3);
230	LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
231
232	LD32(p3, DCPLB_DATA4);
233	LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
234
235
236X3:	[ P1 ] = R1;		// Exception should occur here
237
238
239	// Now check that handler read correct values
240	CHECKREG(r4,0x23);			// supv and EXCPT_PROT
241	CHECKREG(r5, 0x3000);
242	CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER | FAULT_CPLB3));
243	CHECKREG_SYM(r7, X3, r0);			// RETX should be value of X3	(HARDCODED ADDR!!)
244
245	//-------------------------------------------------------
246	// Protection violation - Illegal DAG1 Access
247	// Since this test uses DAG0, there shouldn't be any exception
248	R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
249
250	LD32(p1, 0x4000);
251	LD32(r1, 0xDEADBEEF);
252
253	LD32(p2, DCPLB_DATA4);
254	LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
255
256	LD32(p3, DCPLB_DATA5);
257	LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
258
259
260X4:	[ P1 ] = R1;		// Exception should NOT occur here
261
262
263	// Now check that handler read correct values
264	// Handler shouldn't have been invoked, so registers should
265	// remain unchanged.
266	CHECKREG(r4,0);			// supv and EXCPT_PROT
267	CHECKREG(r5, 0);
268	CHECKREG(r6, 0);
269	CHECKREG(r7, 0);		// RETX should NOT be value of X4	(HARDCODED ADDR!!)
270
271	//-------------------------------------------------------
272	// L1Miss not implemented yet - skip for now....
273
274//	//-------------------------------------------------------
275//	// Protection violation - L1 Miss
276//	r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0;
277//
278//	LD32(p1, 0x5000);
279//	LD32(r1, 0xDEADBEEF);
280//
281//	LD32(p2, DCPLB_DATA5);
282//	LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
283//
284//	LD32(p3, DCPLB_DATA6);
285//	LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR);
286//
287//
288//X5:	//[p1] = r1;		// Exception should occur here
289//	r0 = [p1];
290//
291//
292//	// Now check that handler read correct values
293//	CHECKREG(r4,0x23);			// supv and EXCPT_PROT
294//	CHECKREG(r5, 0x5000);
295//	// CHECKREG(r6, FAULT_DATA | FAULT_CPLB5);
296//	CHECKREG_SYM(r7, X5, r0);			// RETX should be value of X5	(HARDCODED ADDR!!)
297
298
299	//-------------------------------------------------------
300	dbg_pass;
301
302
303handler:
304	// generic protection exception handler
305	// Inputs:
306	//	p2:	addr of CPLB entry to be modified	( current test)
307	//	r2:	new data for CPLB entry
308	//
309	//	p3:	addr of CPLB entry to be modified	( next test)
310	//	r3:	new data for CPLB entry
311	//
312	// Outputs:
313	//	r4:	SEQSTAT
314	//	r5:	DCPLB_FAULT_ADDR
315	//	r6:	DCPLB_STATUS
316	//	r7:	RETX	(instruction addr where exception occurred)
317
318
319	R4 = SEQSTAT;	// Get exception cause
320
321	// read data addr which caused exception
322	RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
323
324	RD_MMR(DCPLB_STATUS, p0, r6);
325
326	R7 = RETX;	// get address of excepting instruction
327
328
329	// modify CPLB to allow access.  Main pgm passes in addr and data
330	[ P2 ] = R2;
331
332	// Set up for next test
333	[ P3 ] = R3;
334
335	NOP;NOP;NOP;NOP;NOP;NOP;NOP;	// in lieu of CSYNC;
336
337	// return from exception and re-execute offending instruction
338	RTX;
339
340	// Nops to work around ICache bug
341	NOP;NOP;NOP;NOP;NOP;
342	NOP;NOP;NOP;NOP;NOP;
343
344
345.section MEM_0x800,"aw"
346	.dd 0x00000000
347	.dd 0x00000000
348	.dd 0x00000000
349	.dd 0x00000000
350
351.section MEM_0x1000,"aw"
352	.dd 0x00000000
353	.dd 0x00000000
354	.dd 0x00000000
355	.dd 0x00000000
356
357.section MEM_0x2000,"aw"
358	.dd 0x00000000
359	.dd 0x00000000
360	.dd 0x00000000
361	.dd 0x00000000
362
363.section MEM_0x3000,"aw"
364	.dd 0x00000000
365	.dd 0x00000000
366	.dd 0x00000000
367	.dd 0x00000000
368
369.section MEM_0x4000,"aw"
370	.dd 0x00000000
371	.dd 0x00000000
372	.dd 0x00000000
373	.dd 0x00000000
374
375.section MEM_0x5000,"aw"
376	.dd 0x00000000
377	.dd 0x00000000
378	.dd 0x00000000
379	.dd 0x00000000
380
381// Need illegal SRAM addr to test CPLB_L1SRAM
382//.data 0x6000
383//	.dd 0x00000000
384//	.dd 0x00000000
385//	.dd 0x00000000
386//	.dd 0x00000000
387
388.section MEM_0x7000,"aw"
389	.dd 0x00000000
390	.dd 0x00000000
391	.dd 0x00000000
392	.dd 0x00000000
393