1//Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
2// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
3//              Supervisor mode
4# mach: bfin
5# sim: --environment operating
6
7#include "test.h"
8.include "testutils.inc"
9start
10
11include(std.inc)
12include(mmrs.inc)
13include(selfcheck.inc)
14
15#ifndef ITABLE
16#define ITABLE           0xF0000000
17#endif
18#ifndef STACKSIZE
19#define STACKSIZE 0x20
20#endif
21
22// This test embeds .text offsets, so pad our test so it lines up.
23.space 0x64
24
25// Boot code
26
27 BOOT :
28INIT_R_REGS(0);                             // Initialize Dregs
29INIT_P_REGS(0);                             // Initialize Pregs
30
31CHECK_INIT(p5,   0x00BFFFFC);
32
33LD32(p0, EVT0);              // Setup Event Vectors and Handlers
34
35LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
36        [ P0 ++ ] = R0;
37
38LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
39        [ P0 ++ ] = R0;
40
41LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
42        [ P0 ++ ] = R0;
43
44LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
45        [ P0 ++ ] = R0;
46
47        [ P0 ++ ] = R0;                // IVT4 not used
48
49LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
50        [ P0 ++ ] = R0;
51
52LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
53        [ P0 ++ ] = R0;
54
55LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
56        [ P0 ++ ] = R0;
57
58LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
59        [ P0 ++ ] = R0;
60
61LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
62        [ P0 ++ ] = R0;
63
64LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
65        [ P0 ++ ] = R0;
66
67LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
68        [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
71        [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
74        [ P0 ++ ] = R0;
75
76LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
77        [ P0 ++ ] = R0;
78
79LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
80        [ P0 ++ ] = R0;
81
82LD32(p0, EVT_OVERRIDE);
83        R0 = 0;
84        [ P0 ++ ] = R0;
85        R0 = -1;     // Change this to mask interrupts (*)
86        [ P0 ] = R0;   // IMASK
87
88LD32_LABEL(p1, START);
89
90LD32(p0, EVT15);
91        [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
92
93LD32_LABEL(r7, DUMMY);
94RETI = r7;
95RAISE 15;    // after we RTI, INT 15 should be taken
96
97NOP;        // Workaround for Bug 217
98RTI;
99NOP;
100NOP;
101NOP;
102DUMMY:
103	  NOP;
104NOP;
105NOP;
106NOP;
107
108// .code 0x200
109START:
110WR_MMR(TBUFCTL, 0x00000001, p0, r0);        // Turn ON trace Buffer
111WR_MMR(TBUFCTL, 0x00000003, p0, r0);        // Turn ON trace Buffer
112                                                    //   TBUFPWR   = 1
113                                                    //   TBUFEN    = 1
114                                                    //   TBUFOVF   = 0
115                                                    //   CMPLP     = 0
116NOP;
117NOP;
118NOP;
119NOP;
120
121// The following code sets up the test for running in USER mode
122
123LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
124                        // ReturnFromInterrupt (RTI)
125RETI = r0;      // We need to load the return address
126
127RTI;
128
129STARTUSER:
130LD32_LABEL(sp, USTACK);   // setup the stack pointer
131FP = SP;            // set frame pointer
132JUMP BEGIN;
133
134//*********************************************************************
135
136BEGIN:
137
138
139NOP;
140	    NOP;
141NOP;
142JUMP.S label1;
143        R4.L = 0x1111;
144        R4.H = 0x1111;
145NOP;
146NOP;
147NOP;
148label2: R5.H = 0x7777;
149        R5.L = 0x7888;
150JUMP.S label3;
151        R6.L = 0x1111;
152        R6.H = 0x1111;
153NOP;
154NOP;
155NOP;
156NOP;
157NOP;
158label1: R4.H = 0x5555;
159        R4.L = 0x6666;
160NOP;
161NOP;
162NOP;
163NOP;
164NOP;
165JUMP.S label2;
166        R5.L = 0x1111;
167        R5.H = 0x1111;
168NOP;
169NOP;
170NOP;
171NOP;
172label3:
173		NOP;
174NOP;
175NOP;
176		NOP;
177		NOP;
178		NOP;
179NOP;
180NOP;
181        // Checks the contents of the Trace Buffer
182
183	    EXCPT 0;
184		NOP; NOP; NOP; NOP;
185CHECKREG(r2,    0x00000006);
186CHECKREG(r1,    0x00000416);
187CHECKREG(r0,    0x000002aa);
188CHECKREG(r3,    0x0000029a);
189CHECKREG(r4,    0x00000262);
190CHECKREG(r5,    0x00000004);
191CHECKREG(r6,    0x0000025a);
192CHECKREG(r7,    0x00000288);
193		NOP; NOP; NOP; NOP;
194		NOP; NOP; NOP; NOP;
195
196		EXCPT 1;
197		NOP; NOP; NOP; NOP;
198		CHECKREG(r2,    0x00000005);
199CHECKREG(r1,    0x00000416);
200CHECKREG(r0,    0x00000304);
201CHECKREG(r3,    0x000002ac);
202CHECKREG(r4,    0x00000470);
203CHECKREG(r5,    0x00000003);
204CHECKREG(r6,    0x00000276);
205CHECKREG(r7,    0x0000024a);
206		NOP; NOP; NOP; NOP;
207		NOP; NOP; NOP; NOP;
208
209		EXCPT 2;
210		NOP; NOP; NOP; NOP;
211		CHECKREG(r2,    0x00000004);
212CHECKREG(r1,    0x00000416);
213CHECKREG(r0,    0x0000035e);
214CHECKREG(r3,    0x00000306);
215CHECKREG(r4,    0x00000470);
216CHECKREG(r5,    0x00000002);
217CHECKREG(r6,    0x00000244);
218CHECKREG(r7,    0x00000242);
219		NOP; NOP; NOP; NOP;
220
221		EXCPT 3;
222		NOP; NOP; NOP; NOP;
223		CHECKREG(r2,    0x00000003);
224CHECKREG(r1,    0x00000416);
225CHECKREG(r0,    0x000003b0);
226CHECKREG(r3,    0x00000360);
227CHECKREG(r4,    0x00000470);
228CHECKREG(r5,    0x00000001);
229CHECKREG(r6,    0x00000238);
230CHECKREG(r7,    0x00000236);
231
232
233
234NOP;
235NOP;
236NOP;
237NOP;
238NOP;
239dbg_pass;        // Call Endtest Macro
240
241
242
243//*********************************************************************
244//
245// Handlers for Events
246//
247
248EHANDLE:            // Emulation Handler 0
249RTE;
250
251RHANDLE:            // Reset Handler 1
252RTI;
253
254NHANDLE:            // NMI Handler 2
255RTN;
256
257XHANDLE:            // Exception Handler 3
258    	R7 = SEQSTAT;
259
260RD_MMR(TBUFSTAT, p0, 	r2);
261RD_MMR(TBUF,    p0,     r1);
262RD_MMR(TBUF,    p0,     r0);
263RD_MMR(TBUF,    p0,     r3);
264RD_MMR(TBUF,    p0,     r4);
265RD_MMR(TBUFSTAT, p0, 	r5);
266RD_MMR(TBUF,    p0,     r6);
267RD_MMR(TBUF,    p0,     r7);
268
269		NOP; NOP; NOP; NOP;
270
271RTX;
272
273		NOP; NOP; NOP; NOP;
274		NOP; NOP; NOP; NOP;
275
276HWHANDLE:           // HW Error Handler 5
277RTI;
278
279THANDLE:            // Timer Handler 6
280RTI;
281
282I7HANDLE:           // IVG 7 Handler
283RTI;
284
285I8HANDLE:           // IVG 8 Handler
286RTI;
287
288I9HANDLE:           // IVG 9 Handler
289RTI;
290
291I10HANDLE:          // IVG 10 Handler
292RTI;
293
294I11HANDLE:          // IVG 11 Handler
295RTI;
296
297I12HANDLE:          // IVG 12 Handler
298RTI;
299
300I13HANDLE:          // IVG 13 Handler
301RTI;
302
303I14HANDLE:          // IVG 14 Handler
304RTI;
305
306I15HANDLE:          // IVG 15 Handler
307RTI;
308
309
310    .space (STACKSIZE);
311KSTACK:
312
313    .space (STACKSIZE);
314USTACK:
315