1//Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp 2# mach: bfin 3# sim: --environment operating 4 5#include "test.h" 6.include "testutils.inc" 7start 8 9include(std.inc) 10include(mmrs.inc) 11include(selfcheck.inc) 12 13#ifndef ITABLE 14#define ITABLE 0xF0000000 15#endif 16 17// This test embeds .text offsets, so pad our test so it lines up. 18.space 0x64 19 20// Boot code 21 22 BOOT : 23INIT_R_REGS(0); // Initialize Dregs 24INIT_P_REGS(0); // Initialize Pregs 25 26CHECK_INIT(p5, 0x00BFFFFC); 27 28 29LD32(p0, EVT0); // Setup Event Vectors and Handlers 30 31LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 32 [ P0 ++ ] = R0; 33 34LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 35 [ P0 ++ ] = R0; 36 37LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 38 [ P0 ++ ] = R0; 39 40LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 41 [ P0 ++ ] = R0; 42 43 [ P0 ++ ] = R0; // IVT4 not used 44 45LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 46 [ P0 ++ ] = R0; 47 48LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 49 [ P0 ++ ] = R0; 50 51LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 52 [ P0 ++ ] = R0; 53 54LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 55 [ P0 ++ ] = R0; 56 57LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 58 [ P0 ++ ] = R0; 59 60LD32_LABEL(r0, I10HANDLE); // IVG10 Handler 61 [ P0 ++ ] = R0; 62 63LD32_LABEL(r0, I11HANDLE); // IVG11 Handler 64 [ P0 ++ ] = R0; 65 66LD32_LABEL(r0, I12HANDLE); // IVG12 Handler 67 [ P0 ++ ] = R0; 68 69LD32_LABEL(r0, I13HANDLE); // IVG13 Handler 70 [ P0 ++ ] = R0; 71 72LD32_LABEL(r0, I14HANDLE); // IVG14 Handler 73 [ P0 ++ ] = R0; 74 75LD32_LABEL(r0, I15HANDLE); // IVG15 Handler 76 [ P0 ++ ] = R0; 77 78LD32(p0, EVT_OVERRIDE); 79 R0 = 0; 80 [ P0 ++ ] = R0; 81 R0 = -1; // Change this to mask interrupts (*) 82 [ P0 ] = R0; // IMASK 83 84LD32_LABEL(p1, START); 85 86LD32(p0, EVT15); 87 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 88 89LD32_LABEL(r7, DUMMY); 90RETI = r7; 91RAISE 15; // after we RTI, INT 15 should be taken 92 93NOP; // Workaround for Bug 217 94RTI; 95NOP; 96NOP; 97NOP; 98DUMMY: 99 NOP; 100NOP; 101NOP; 102NOP; 103 104 105 106 START : 107 108WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer 109WR_MMR(TBUFCTL, 0x0000000b, p0, r0); // Turn ON trace Buffer 110 // TBUFPWR = 1 111 // TBUFEN = 1 112 // TBUFOVF = 0 113 // CMPLP = 01 114NOP; 115NOP; 116NOP; 117 NOP; 118 NOP; 119 R6 = 0; 120 R7 = 10; 121 122JMP: 123 JUMP.S LABEL0; 124 NOP; 125 NOP; 126 127LABEL0: 128 P1 = 0x0006; 129 JUMP (PC+P1); 130 131LABEL1: 132 LD32(R3, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> 133 134LABEL2: 135 CC = R7 == R6; 136 IF CC JUMP END; 137 R6 += 1; 138 JUMP LABEL2; 139 140LABEL3: 141 NOP; 142 143LABEL4: 144 LD32(R4, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> 145 146 147 148 149END: 150 R0 = 1; 151 NOP; 152 NOP; 153 NOP; 154 155CHECKREG(r3, 0x00000000); 156CHECKREG(r4, 0x00000000); 157 // Read the contents of the Trace Buffer 158 159RD_MMR(TBUFSTAT, p0, r0); 160CHECKREG(r0, 0x00000004); 161 162 // Read last entry of the Trace Buffer 163RD_MMR(TBUF, p0, r1); 164CHECKREG(r1, 0x00000256); 165 166RD_MMR(TBUF, p0, r2); 167CHECKREG(r2, 0x00000246); 168 169RD_MMR(TBUFSTAT, p0, r0); 170CHECKREG(r0, 0x00000003); 171 172 // Read last entry of the Trace Buffer 173RD_MMR(TBUF, p0, r1); 174CHECKREG(r1, 0x00000245); 175 176RD_MMR(TBUF, p0, r2); 177CHECKREG(r2, 0x0000024a); 178 179RD_MMR(TBUFSTAT, p0, r0); 180CHECKREG(r0, 0x00000002); 181 182 // Read last entry of the Trace Buffer 183RD_MMR(TBUF, p0, r1); 184CHECKREG(r1, 0x00000240); 185 186RD_MMR(TBUF, p0, r2); 187CHECKREG(r2, 0x0000023a); 188 189RD_MMR(TBUFSTAT, p0, r0); 190CHECKREG(r0, 0x00000001); 191 192 // Read last entry of the Trace Buffer 193RD_MMR(TBUF, p0, r1); 194CHECKREG(r1, 0x00000238); 195 196RD_MMR(TBUF, p0, r2); 197CHECKREG(r2, 0x00000232); 198 199 200 201NOP; 202NOP; 203NOP; 204NOP; 205NOP; 206NOP; 207dbg_pass; // Call Endtest Macro 208 209 210 211//********************************************************************* 212// 213// Handlers for Events 214// 215 216EHANDLE: // Emulation Handler 0 217RTE; 218 219RHANDLE: // Reset Handler 1 220RTI; 221 222NHANDLE: // NMI Handler 2 223RTN; 224 225XHANDLE: // Exception Handler 3 226 227RTX; 228 NOP;NOP;NOP;NOP;NOP; 229 NOP;NOP;NOP;NOP;NOP; 230 231HWHANDLE: // HW Error Handler 5 232RTI; 233 234THANDLE: // Timer Handler 6 235RTI; 236 237I7HANDLE: // IVG 7 Handler 238RTI; 239 240I8HANDLE: // IVG 8 Handler 241RTI; 242 243I9HANDLE: // IVG 9 Handler 244RTI; 245 246I10HANDLE: // IVG 10 Handler 247RTI; 248 249I11HANDLE: // IVG 11 Handler 250RTI; 251 252I12HANDLE: // IVG 12 Handler 253RTI; 254 255I13HANDLE: // IVG 13 Handler 256RTI; 257 258I14HANDLE: // IVG 14 Handler 259RTI; 260 261I15HANDLE: // IVG 15 Handler 262RTI; 263