1//Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp
2// Spec Reference: mmr timer
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(gen_int.inc)
11include(selfcheck.inc)
12include(std.inc)
13include(mmrs.inc)
14
15#ifndef STACKSIZE
16#define STACKSIZE 0x10
17#endif
18//
19
20////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
21
22//
23// Reset/Bootstrap Code
24//   (Here we set the processor operating modes, initialize registers
25//    etc.)
26//
27
28BOOT:
29
30INIT_R_REGS(0);
31INIT_P_REGS(0);
32INIT_I_REGS(0);     // initialize the dsp address regs
33INIT_M_REGS(0);
34INIT_L_REGS(0);
35INIT_B_REGS(0);
36    //CHECK_INIT(p5, 0xe0000000);
37include(symtable.inc)
38CHECK_INIT_DEF(p5);
39
40CLI R1;           // inhibit events during MMR writes
41
42LD32_LABEL(sp, USTACK);   // setup the user stack pointer
43USP = SP;                  // and frame pointer
44
45LD32_LABEL(sp, KSTACK);   // setup the stack pointer
46FP = SP;                  // and frame pointer
47
48LD32(p0, EVT0);      // Setup Event Vectors and Handlers
49LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
50    [ P0 ++ ] = R0;
51
52LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
53    [ P0 ++ ] = R0;
54
55LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
56    [ P0 ++ ] = R0;
57
58LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
59    [ P0 ++ ] = R0;
60
61    [ P0 ++ ] = R0;          // EVT4 not used global Interr Enable (INT4)
62
63LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
64    [ P0 ++ ] = R0;
65
66LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
67    [ P0 ++ ] = R0;
68LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
69    [ P0 ++ ] = R0;
70
71LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
72    [ P0 ++ ] = R0;
73
74LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
75    [ P0 ++ ] = R0;
76
77LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
78    [ P0 ++ ] = R0;
79
80LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
81    [ P0 ++ ] = R0;
82
83LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
84    [ P0 ++ ] = R0;
85
86LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
87    [ P0 ++ ] = R0;
88
89LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
90    [ P0 ++ ] = R0;
91
92LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
93    [ P0 ++ ] = R0;
94
95LD32(p0, EVT_OVERRIDE);
96    R0 = 0;
97    [ P0 ++ ] = R0;
98
99    R1 = -1;     // Change this to mask interrupts (*)
100CSYNC;       // wait for MMR writes to finish
101STI R1;      // sync and reenable events (implicit write to IMASK)
102
103DUMMY:
104
105    R0 = 0 (Z);
106
107LT0 = r0;       // set loop counters to something deterministic
108LB0 = r0;
109LC0 = r0;
110LT1 = r0;
111LB1 = r0;
112LC1 = r0;
113
114ASTAT = r0;     // reset other internal regs
115SYSCFG = r0;
116RETS = r0;      // prevent X's breaking LINK instruction
117
118// The following code sets up the test for running in USER mode
119
120LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
121                        // ReturnFromInterrupt (RTI)
122RETI = r0;      // We need to load the return address
123
124// Comment the following line for a USER Mode test
125
126JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
127
128RTI;
129
130STARTSUP:
131LD32_LABEL(p1, BEGIN);
132
133LD32(p0, EVT15);
134
135CLI R1;    // inhibit events during write to MMR
136    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
137CSYNC;       // wait for it
138STI R1;      // reenable events with proper imask
139
140RAISE 15;       // after we RTI, INT 15 should be taken
141
142RTI;
143
144//
145// The Main Program
146//
147STARTUSER:
148LINK 0;     // change for how much stack frame space you need.
149
150JUMP BEGIN;
151
152
153//*********************************************************************
154
155BEGIN:
156
157                // COMMENT the following line for USER MODE tests
158    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
159
160                // **** YOUR CODE GOES HERE ****
161
162    // TCNTL: 4 bits, rw=1          = 0xFFE03000
163LD32(p0, 0xFFE03000);
164LD32(r0, 0x0000000D);
165    [ P0 ] = R0;
166CSYNC;                  // without this it read out zero
167    R1 = [ P0 ];
168
169    // TPERIOD: 32 bits, rw=1       = 0xFFE03004
170LD32(p0, 0xFFE03004);
171LD32(r0, 0x11112222);
172    [ P0 ] = R0;
173CSYNC;                  // without this it read out zero
174    R2 = [ P0 ];
175
176    // TSCALE: 8 bits, rw=1         = 0xFFE03008
177LD32(p0, 0xFFE03008);
178LD32(r0, 0x00000050);
179    [ P0 ] = R0;
180CSYNC;                  // without this it read out zero
181    R3 = [ P0 ];
182
183
184    //  TCOUNT: 32 bits, rw=1       = 0xFFE0300C
185LD32(p0, 0xFFE0300C);
186LD32(r0, 0x00000100);
187    [ P0 ] = R0;
188CSYNC;                  // without this it read out zero
189    R4 = [ P0 ];
190
191
192CHECKREG(r1, 0x0000000D);
193CHECKREG(r2, 0x11112222);
194CHECKREG(r3, 0x00000050);
195CHECKREG(r4, 0x00000100);
196
197dbg_pass;            // End the test
198
199//*********************************************************************
200
201//
202// Handlers for Events
203//
204
205EHANDLE:            // Emulation Handler 0
206RTE;
207
208RHANDLE:            // Reset Handler 1
209RTI;
210
211NHANDLE:            // NMI Handler 2
212    R0 = 2;
213RTN;
214
215XHANDLE:            // Exception Handler 3
216
217RTX;
218
219HWHANDLE:           // HW Error Handler 5
220    R2 = 5;
221RTI;
222
223THANDLE:            // Timer Handler 6
224    R3 = 6;
225RTI;
226
227I7HANDLE:           // IVG 7 Handler
228    R4 = 7;
229RTI;
230
231I8HANDLE:           // IVG 8 Handler
232    R5 = 8;
233RTI;
234
235I9HANDLE:           // IVG 9 Handler
236    R6 = 9;
237RTI;
238
239I10HANDLE:          // IVG 10 Handler
240    R7 = 10;
241RTI;
242
243I11HANDLE:          // IVG 11 Handler
244    R0 = 11;
245RTI;
246
247I12HANDLE:          // IVG 12 Handler
248    R1 = 12;
249RTI;
250
251I13HANDLE:          // IVG 13 Handler
252    R2 = 13;
253RTI;
254
255I14HANDLE:          // IVG 14 Handler
256    R3 = 14;
257RTI;
258
259I15HANDLE:          // IVG 15 Handler
260    R4 = 15;
261RTI;
262
263NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
264
265//
266// Data Segment
267//
268
269.data
270DATA:
271    .space (0x10);
272
273// Stack Segments (Both Kernel and User)
274
275    .space (STACKSIZE);
276KSTACK:
277
278    .space (STACKSIZE);
279USTACK:
280
281//.data 0xFFE03000
282//.dd 0x00000000
283