1//Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp
2// Spec Reference: mmr ppop illegal address
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(gen_int.inc)
11include(selfcheck.inc)
12include(std.inc)
13include(mmrs.inc)
14
15#ifndef STACKSIZE
16#define STACKSIZE 0x10
17#endif
18#ifndef ITABLE
19#define ITABLE 0xF0000000
20#endif
21
22GEN_INT_INIT(ITABLE) // set location for interrupt table
23
24//
25// Reset/Bootstrap Code
26//   (Here we set the processor operating modes, initialize registers
27//    etc.)
28//
29
30BOOT:
31
32INIT_R_REGS(0);
33INIT_P_REGS(0);
34INIT_I_REGS(0);     // initialize the dsp address regs
35INIT_M_REGS(0);
36INIT_L_REGS(0);
37INIT_B_REGS(0);
38    //CHECK_INIT(p5, 0xe0000000);
39include(symtable.inc)
40CHECK_INIT_DEF(p5);
41
42CLI R1;           // inhibit events during MMR writes
43
44LD32_LABEL(sp, USTACK);   // setup the user stack pointer
45USP = SP;                  // and frame pointer
46
47LD32_LABEL(sp, KSTACK);   // setup the stack pointer
48FP = SP;                  // and frame pointer
49
50LD32(p0, EVT0);      // Setup Event Vectors and Handlers
51LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
52    [ P0 ++ ] = R0;
53
54LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
55    [ P0 ++ ] = R0;
56
57LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
58    [ P0 ++ ] = R0;
59
60LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
61    [ P0 ++ ] = R0;
62
63    [ P0 ++ ] = R0;          // EVT4 not used global Interr Enable (INT4)
64
65LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
66    [ P0 ++ ] = R0;
67
68LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
69    [ P0 ++ ] = R0;
70
71LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
72    [ P0 ++ ] = R0;
73
74LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
75    [ P0 ++ ] = R0;
76
77LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
78    [ P0 ++ ] = R0;
79
80LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
81    [ P0 ++ ] = R0;
82
83LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
84    [ P0 ++ ] = R0;
85
86LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
87    [ P0 ++ ] = R0;
88
89LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
90    [ P0 ++ ] = R0;
91
92LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
93    [ P0 ++ ] = R0;
94
95LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
96    [ P0 ++ ] = R0;
97
98LD32(p0, EVT_OVERRIDE);
99    R0 = 0;
100    [ P0 ++ ] = R0;
101
102    R1 = -1;     // Change this to mask interrupts (*)
103CSYNC;       // wait for MMR writes to finish
104STI R1;      // sync and reenable events (implicit write to IMASK)
105
106DUMMY:
107
108    R0 = 0 (Z);
109
110LT0 = r0;       // set loop counters to something deterministic
111LB0 = r0;
112LC0 = r0;
113LT1 = r0;
114LB1 = r0;
115LC1 = r0;
116
117ASTAT = r0;     // reset other internal regs
118SYSCFG = r0;
119RETS = r0;      // prevent X's breaking LINK instruction
120
121// The following code sets up the test for running in USER mode
122
123LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
124                        // ReturnFromInterrupt (RTI)
125RETI = r0;      // We need to load the return address
126
127// Comment the following line for a USER Mode test
128
129JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
130
131RTI;
132
133STARTSUP:
134LD32_LABEL(p1, BEGIN);
135
136LD32(p0, EVT15);
137
138CLI R1;    // inhibit events during write to MMR
139    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
140CSYNC;       // wait for it
141STI R1;      // reenable events with proper imask
142
143RAISE 15;       // after we RTI, INT 15 should be taken
144
145RTI;
146
147//
148// The Main Program
149//
150STARTUSER:
151LINK 0;     // change for how much stack frame space you need.
152
153JUMP BEGIN;
154
155
156
157//*********************************************************************
158
159BEGIN:
160
161                // COMMENT the following line for USER MODE tests
162    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
163
164                // **** YOUR CODE GOES HERE ****
165
166LD32(r0, 0206037020);
167LD32(r1, 0x10070030);
168LD32(r2, 0xe2000043);
169LD32(r3, 0x30305050);
170LD32(r4, 0x0f040860);
171LD32(r5, 0x0a0050d0);
172LD32(r6, 0x00000000);
173LD32(r7, 0x0f060071);
174//    LD32(sp, 0xFFE02104);
175//  [--sp] = (r7-r6);
176    [ -- SP ] = R7;
177    [ -- SP ] = R6;
178.dd 0xffff
179    R1 += 2;
180
181CHECKREG(r1, 0x10070034);
182CHECKREG(r2, 0xE2000046);
183CHECKREG(r3, 0x30305054);
184CHECKREG(r4, 0x0f040865);
185CHECKREG(r5, 0x0a0050d6);
186CHECKREG(r6, 0x00000007);
187CHECKREG(r7, 0x0f060079);
188    R7 = [ SP ++ ];
189CHECKREG(r7, 0x00000000);
190
191dbg_pass;            // End the test
192
193//*********************************************************************
194
195//
196// Handlers for Events
197//
198
199EHANDLE:            // Emulation Handler 0
200RTE;
201
202RHANDLE:            // Reset Handler 1
203RTI;
204
205NHANDLE:            // NMI Handler 2
206    R0 = 2;
207RTN;
208
209XHANDLE:            // Exception Handler 3
210R0 = RETX;   // error handler:RETX has the address of the same Illegal instr
211    R1 += 2;
212    R2 += 3;
213    R3 += 4;
214    R4 += 5;
215    R5 += 6;
216    R6 += 7;
217    R7 += 8;
218R0 += 2;     // we have to add 2 to point to next instr after return (16-bit illegal instr)
219RETX = R0;
220NOP; NOP; NOP; NOP;
221
222
223RTX;
224
225HWHANDLE:           // HW Error Handler 5
226    R2 = 5;
227RTI;
228
229THANDLE:            // Timer Handler 6
230    R3 = 6;
231RTI;
232
233I7HANDLE:           // IVG 7 Handler
234    R4 = 7;
235RTI;
236
237I8HANDLE:           // IVG 8 Handler
238    R5 = 8;
239RTI;
240
241I9HANDLE:           // IVG 9 Handler
242    R6 = 9;
243RTI;
244
245I10HANDLE:          // IVG 10 Handler
246    R7 = 10;
247RTI;
248
249I11HANDLE:          // IVG 11 Handler
250    R0 = 11;
251RTI;
252
253I12HANDLE:          // IVG 12 Handler
254    R1 = 12;
255RTI;
256
257I13HANDLE:          // IVG 13 Handler
258    R2 = 13;
259RTI;
260
261I14HANDLE:          // IVG 14 Handler
262    R3 = 14;
263RTI;
264
265I15HANDLE:          // IVG 15 Handler
266    R4 = 15;
267RTI;
268
269NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
270
271//
272// Data Segment
273//
274
275.section MEM_DATA_ADDR_1,"aw"
276DATA0:
277.dd 0x000a0000
278.dd 0x000b0001
279.dd 0x000c0002
280.dd 0x000d0003
281.dd 0x000e0004
282.dd 0x000f0005
283.dd 0x00100006
284.dd 0x00200007
285.dd 0x00300008
286.dd 0x00400009
287.dd 0x0050000a
288.dd 0x0060000b
289.dd 0x0070000c
290.dd 0x0080000d
291.dd 0x0090000e
292.dd 0x0100000f
293.dd 0x02000010
294.dd 0x03000011
295.dd 0x04000012
296.dd 0x05000013
297.dd 0x06000014
298.dd 0x001a0000
299.dd 0x001b0001
300.dd 0x001c0002
301// Stack Segments (Both Kernel and User)
302
303    .space (STACKSIZE);
304KSTACK:
305
306    .space (STACKSIZE);
307USTACK:
308