1//Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp 2// Spec Reference: interrupt on HW TIMER tscale 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10// 11// Include Files 12// 13 14include(std.inc) 15include(selfcheck.inc) 16 17// Defines 18 19#ifndef TCNTL 20#define TCNTL 0xFFE03000 21#endif 22#ifndef TPERIOD 23#define TPERIOD 0xFFE03004 24#endif 25#ifndef TSCALE 26#define TSCALE 0xFFE03008 27#endif 28#ifndef TCOUNT 29#define TCOUNT 0xFFE0300c 30#endif 31#ifndef EVT 32#define EVT 0xFFE02000 33#endif 34#ifndef EVT15 35#define EVT15 0xFFE0203c 36#endif 37#ifndef EVT_OVERRIDE 38#define EVT_OVERRIDE 0xFFE02100 39#endif 40#ifndef ITABLE 41#define ITABLE 0x000FF000 42#endif 43#ifndef PROGRAM_STACK 44#define PROGRAM_STACK 0x000FF100 45#endif 46#ifndef STACKSIZE 47#define STACKSIZE 0x00000300 48#endif 49 50// Boot code 51 52 BOOT : 53INIT_R_REGS(0); // Initialize Dregs 54INIT_P_REGS(0); // Initialize Pregs 55 56 // CHECK_INIT(p5, 0x00BFFFFC); 57 // CHECK_INIT(p5, 0xE0000000); 58include(symtable.inc) 59CHECK_INIT_DEF(p5); 60 61 62LD32(sp, 0x000FF200); 63LD32(p0, EVT); // Setup Event Vectors and Handlers 64 65LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 66 [ P0 ++ ] = R0; 67 68LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 69 [ P0 ++ ] = R0; 70 71LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 72 [ P0 ++ ] = R0; 73 74LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 75 [ P0 ++ ] = R0; 76 77 [ P0 ++ ] = R0; // IVT4 not used 78 79LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 80 [ P0 ++ ] = R0; 81 82LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 83 [ P0 ++ ] = R0; 84 85LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 86 [ P0 ++ ] = R0; 87 88LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 89 [ P0 ++ ] = R0; 90 91LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 92 [ P0 ++ ] = R0; 93 94LD32_LABEL(r0, I10HANDLE); // IVG10 Handler 95 [ P0 ++ ] = R0; 96 97LD32_LABEL(r0, I11HANDLE); // IVG11 Handler 98 [ P0 ++ ] = R0; 99 100LD32_LABEL(r0, I12HANDLE); // IVG12 Handler 101 [ P0 ++ ] = R0; 102 103LD32_LABEL(r0, I13HANDLE); // IVG13 Handler 104 [ P0 ++ ] = R0; 105 106LD32_LABEL(r0, I14HANDLE); // IVG14 Handler 107 [ P0 ++ ] = R0; 108 109LD32_LABEL(r0, I15HANDLE); // IVG15 Handler 110 [ P0 ++ ] = R0; 111 112LD32(p0, EVT_OVERRIDE); 113 R0 = 0; 114 [ P0 ++ ] = R0; 115 R0 = -1; // Change this to mask interrupts (*) 116 [ P0 ] = R0; // IMASK 117 118LD32_LABEL(p1, START); 119 120LD32(p0, EVT15); 121 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 122CSYNC; 123RAISE 15; // after we RTI, INT 15 should be taken 124 125LD32_LABEL(r7, START); 126RETI = r7; 127NOP; // Workaround for Bug 217 128RTI; 129NOP; 130NOP; 131 132//.code 0x200 133 START : 134 R7 = 0x0; 135 R6 = 0x1; 136 [ -- SP ] = RETI; // Enable Nested Interrupts 137 138WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) 139WR_MMR(TPERIOD, 0x00000010, p0, r0); 140WR_MMR(TCOUNT, 0x00000002, p0, r0); 141WR_MMR(TSCALE, 0x00000001, p0, r0); 142CSYNC; 143 // Read the contents of the Timer 144RD_MMR(TPERIOD, p0, r2); 145CHECKREG(r2, 0x00000010); 146 147RD_MMR(TCOUNT, p0, r3); 148CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace -seed 8b8db910 149 150 151WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) 152CSYNC; 153 154RD_MMR(TCOUNT, p0, r4); 155CHECKREG(r4, 0x00000000); 156 157RD_MMR(TCNTL, p0, r5); 158CHECKREG(r5, 0x0000000B); 159 160WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer 161CSYNC; 162CHECKREG(r7, 0x00000001); 163 R7 = 0; 164NOP; 165WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power 166WR_MMR(TPERIOD, 0x00000010, p0, r0); 167WR_MMR(TCOUNT, 0x00000003, p0, r0); 168WR_MMR(TSCALE, 0x00000128, p0, r0); 169WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer 170CSYNC; 171NOP; 172NOP; 173label5: R5.H = 0x7777; 174 R5.L = 0x7888; 175JUMP.S label6; 176 R5.L = 0x1111; // Will be killed 177 R5.H = 0x1111; // Will be killed 178NOP; 179label4: R4.H = 0x5555; 180 R4.L = 0x6666; 181NOP; 182JUMP.S label5; 183 R5.L = 0x2222; // Will be killed 184 R5.H = 0x2222; // Will be killed 185NOP; 186label6: R3.H = 0x7999; 187 R3.L = 0x7aaa; 188NOP; 189 // With auto reload 190 // Read the contents of the Timer 191 192RD_MMR(TPERIOD, p0, r2); 193CHECKREG(r2, 0x00000010); 194 195RD_MMR(TCNTL , p0, r3); 196CHECKREG(r3, 0x0000000b); 197 198CHECKREG(r7, 0x00000001); 199 200WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn ON Timer auto-reload 201WR_MMR(TPERIOD, 0x00000020, p0, r0); 202WR_MMR(TSCALE, 0x00000003, p0, r0); 203WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto-reload 204 205NOP; NOP; 206 R7 = 0; 207CSYNC; 208 209NOP; NOP; NOP; NOP; NOP; NOP; 210NOP; NOP; NOP; NOP; NOP; NOP; 211NOP; NOP; NOP; NOP; NOP; NOP; 212NOP; NOP; NOP; NOP; NOP; NOP; 213NOP; NOP; NOP; NOP; NOP; NOP; 214NOP; NOP; NOP; NOP; NOP; NOP; 215NOP; NOP; NOP; NOP; NOP; NOP; 216NOP; NOP; NOP; NOP; NOP; NOP; 217NOP; NOP; NOP; NOP; NOP; NOP; 218NOP; NOP; NOP; NOP; NOP; NOP; 219NOP; NOP; NOP; NOP; NOP; NOP; 220NOP; NOP; NOP; NOP; NOP; NOP; 221NOP; NOP; NOP; NOP; NOP; NOP; 222NOP; NOP; NOP; NOP; NOP; NOP; 223NOP; NOP; NOP; NOP; NOP; NOP; 224 R1 = 1; 225 R2 = 1; 226 R3 = 2; 227RD_MMR(TCNTL, p0, r5); 228CHECKREG(r5, 0x0000000F); 229CC = R1 < R7; 230IF CC R2 = R3; 231 232CHECKREG(r2, 0x00000002); 233 234WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer 235CSYNC; 236NOP; NOP; NOP; 237 238 239 240 241 242dbg_pass; // Call Endtest Macro 243 244 245 246//********************************************************************* 247// 248// Handlers for Events 249// 250 251EHANDLE: // Emulation Handler 0 252RTE; 253 254RHANDLE: // Reset Handler 1 255RTI; 256 257NHANDLE: // NMI Handler 2 258RTN; 259 260XHANDLE: // Exception Handler 3 261RTX; 262 263HWHANDLE: // HW Error Handler 5 264RTI; 265 266THANDLE: // Timer Handler 6 267 R7 = R7 + R6; 268RTI; 269 270I7HANDLE: // IVG 7 Handler 271RTI; 272 273I8HANDLE: // IVG 8 Handler 274RTI; 275 276I9HANDLE: // IVG 9 Handler 277RTI; 278 279I10HANDLE: // IVG 10 Handler 280RTI; 281 282I11HANDLE: // IVG 11 Handler 283RTI; 284 285I12HANDLE: // IVG 12 Handler 286RTI; 287 288I13HANDLE: // IVG 13 Handler 289RTI; 290 291I14HANDLE: // IVG 14 Handler 292RTI; 293 294I15HANDLE: // IVG 15 Handler 295 R5 = RETI; 296 P0 = R5; 297JUMP ( P0 ); 298RTI; 299 300.section MEM_DATA_ADDR_1,"aw" 301 302.space (STACKSIZE); 303STACK: 304NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 305