1//Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp
2// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!)
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(gen_int.inc)
11include(selfcheck.inc)
12include(std.inc)
13
14#ifndef STACKSIZE
15#define STACKSIZE 0x10
16#endif
17#ifndef EVT
18#define EVT  0xFFE02000
19#endif
20#ifndef EVT15
21#define EVT15  0xFFE0203C
22#endif
23#ifndef EVT_OVERRIDE
24#define EVT_OVERRIDE 0xFFE02100
25#endif
26//
27
28////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
29
30//
31// Reset/Bootstrap Code
32//   (Here we should set the processor operating modes, initialize registers,
33//    etc.)
34//
35
36BOOT:
37INIT_R_REGS(0);     // initialize general purpose regs
38
39INIT_P_REGS(0);     // initialize the pointers
40
41INIT_I_REGS(0);     // initialize the dsp address regs
42INIT_M_REGS(0);
43INIT_L_REGS(0);
44INIT_B_REGS(0);
45//    CHECK_INIT(p2, 0x2000);
46include(symtable.inc)
47CHECK_INIT_DEF(p2);
48
49
50LD32_LABEL(sp, KSTACK);   // setup the stack pointer
51FP = SP;        // and frame pointer
52
53LD32(p0, EVT);      // Setup Event Vectors and Handlers
54
55LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
56    [ P0 ++ ] = R0;
57
58LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
59    [ P0 ++ ] = R0;
60
61LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
62    [ P0 ++ ] = R0;
63
64LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
65    [ P0 ++ ] = R0;
66
67    [ P0 ++ ] = R0;        // IVT4 not used
68
69LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
70    [ P0 ++ ] = R0;
71
72LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
73    [ P0 ++ ] = R0;
74
75LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
76    [ P0 ++ ] = R0;
77
78LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
79    [ P0 ++ ] = R0;
80
81LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
82    [ P0 ++ ] = R0;
83
84LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
85    [ P0 ++ ] = R0;
86
87LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
88    [ P0 ++ ] = R0;
89
90LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
91    [ P0 ++ ] = R0;
92
93LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
94    [ P0 ++ ] = R0;
95
96LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
97    [ P0 ++ ] = R0;
98
99LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
100    [ P0 ++ ] = R0;
101
102LD32(p0, EVT_OVERRIDE);
103    R0 = 0;
104    [ P0 ++ ] = R0;
105    R0 = -1;     // Change this to mask interrupts (*)
106    [ P0 ] = R0;   // IMASK
107
108DUMMY:
109
110    R0 = 0 (Z);
111
112LT0 = r0;       // set loop counters to something deterministic
113LB0 = r0;
114LC0 = r0;
115LT1 = r0;
116LB1 = r0;
117LC1 = r0;
118
119ASTAT = r0;     // reset other internal regs
120    R0 = 1;
121SYSCFG = r0;    // Enable Supervisor Single Step
122    R4 = 0;
123
124LD32_LABEL(r0, START);
125RETI = r0;      // We need to load the return address
126
127RTI;
128
129
130START:
131LD32_LABEL(sp, USTACK);   // setup the stack pointer
132FP = SP;            // set frame pointer
133JUMP BEGIN;
134
135//*********************************************************************
136
137BEGIN:
138
139    R0 = 0;
140    R1 = 1;
141    R2 = 2;
142    R3 = 3;
143    R5 = 5;
144    R6 = 6;
145    R7 = 7;
146
147EXCPT 3;            // turn off single step via handler
148
149CHECKREG(r4, 0x0b); // 11 instrs are executed before single step = disabled
150CHECKREG(r0, 0x00);
151CHECKREG(r1, 0x03);
152CHECKREG(r2, 0x10);
153CHECKREG(r3, 0x04);
154CHECKREG(r5, 0x09);
155CHECKREG(r6, 0x06);
156CHECKREG(r7, 0x07);
157
158
159    // PUT YOUR TEST HERE!
160
161
162END:
163dbg_pass;            // End the test
164
165//*********************************************************************
166
167//
168// Handlers for Events
169//
170
171EHANDLE:            // Emulation Handler 0
172RTE;
173
174RHANDLE:            // Reset Handler 1
175RTI;
176
177NHANDLE:            // NMI Handler 2
178RTN;
179
180XHANDLE:            // Exception Handler 3
181    [ -- SP ] = ASTAT; // save ASTAT
182    R1 = SEQSTAT;
183    R1 <<= 26;
184    R1 >>= 26;      // only want EXCAUSE
185    R2 = 0x10;      // EXCAUSE 0x10 means Single Step (exception)
186CC = r1 == r2;
187IF CC JUMP SSCOUNT;  // Go to Single Step Handler
188
189SYSCFG = r0;      // otherwise must be an EXCPT, so turn off singlestep
190    R3 += 1;
191
192JUMP.S EXIT;
193
194SSCOUNT:
195    R4 += 1;        // R4 counts single step events
196
197EXIT:
198ASTAT = [sp++];
199    R5 += 1;
200
201RTX;
202
203HWHANDLE:           // HW Error Handler 5
204RTI;
205
206THANDLE:            // Timer Handler 6
207RTI;
208
209I7HANDLE:           // IVG 7 Handler
210RTI;
211
212I8HANDLE:           // IVG 8 Handler
213RTI;
214
215I9HANDLE:           // IVG 9 Handler
216RTI;
217
218I10HANDLE:          // IVG 10 Handler
219RTI;
220
221I11HANDLE:          // IVG 11 Handler
222RTI;
223
224I12HANDLE:          // IVG 12 Handler
225RTI;
226
227I13HANDLE:          // IVG 13 Handler
228RTI;
229
230I14HANDLE:          // IVG 14 Handler
231RTI;
232
233I15HANDLE:          // IVG 15 Handler
234RTI;
235
236NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
237
238//
239// Data Segment
240//
241
242.data
243DATA:
244    .space (0x10);
245
246// Stack Segments (Both Kernel and User)
247
248    .space (STACKSIZE);
249KSTACK:
250
251    .space (STACKSIZE);
252USTACK:
253