1//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp 2// Spec Reference: dsp32shift ashift s 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8// ashift : mix data, count (+)= (half reg) 9// d_reg = ashift (d BY d_lo) 10// Rx by RLx 11 imm32 r0, 0x01230001; 12 imm32 r1, 0x12345678; 13 imm32 r2, 0x23456789; 14 imm32 r3, 0x3456789a; 15 imm32 r4, 0x856789ab; 16 imm32 r5, 0x96789abc; 17 imm32 r6, 0xa789abcd; 18 imm32 r7, 0xb89abcde; 19 R4 = ASHIFT R0 BY R0.L (S); 20 R5 = ASHIFT R1 BY R0.L (S); 21 R6 = ASHIFT R2 BY R0.L (S); 22 R7 = ASHIFT R3 BY R0.L (S); 23 CHECKREG r4, 0x02460002; 24 CHECKREG r5, 0x2468ACF0; 25 CHECKREG r6, 0x468ACF12; 26 CHECKREG r7, 0x68ACF134; 27 28 imm32 r0, 0x01230002; 29 imm32 r1, 0x12345678; 30 imm32 r2, 0x23456789; 31 imm32 r3, 0x3456789a; 32 imm32 r4, 0x956789ab; 33 imm32 r5, 0xa6789abc; 34 imm32 r6, 0xb789abcd; 35 imm32 r7, 0xc89abcde; 36 R1.L = 5; 37 R5 = ASHIFT R0 BY R1.L (S); 38 R6 = ASHIFT R1 BY R1.L (S); 39 R7 = ASHIFT R2 BY R1.L (S); 40 R4 = ASHIFT R3 BY R1.L (S); 41 CHECKREG r4, 0x7FFFFFFF; 42 CHECKREG r5, 0x24600040; 43 CHECKREG r6, 0x7FFFFFFF; 44 CHECKREG r7, 0x7FFFFFFF; 45 46 imm32 r0, 0x01230002; 47 imm32 r1, 0x12345678; 48 imm32 r2, 0x23456789; 49 imm32 r3, 0x3456789a; 50 imm32 r4, 0x456789ab; 51 imm32 r5, 0x56789abc; 52 imm32 r6, 0x6789abcd; 53 imm32 r7, 0x789abcde; 54 R2 = 14; 55 R6 = ASHIFT R0 BY R2.L (S); 56 R7 = ASHIFT R1 BY R2.L (S); 57 R4 = ASHIFT R2 BY R2.L (S); 58 R5 = ASHIFT R3 BY R2.L (S); 59 CHECKREG r4, 0x00038000; 60 CHECKREG r5, 0x7FFFFFFF; 61 CHECKREG r6, 0x7FFFFFFF; 62 CHECKREG r7, 0x7FFFFFFF; 63 64 imm32 r0, 0x01230002; 65 imm32 r1, 0x12345678; 66 imm32 r2, 0x23456789; 67 imm32 r3, 0x3456789a; 68 imm32 r4, 0xa56789ab; 69 imm32 r5, 0xb6789abc; 70 imm32 r6, 0xc789abcd; 71 imm32 r7, 0xd89abcde; 72 R3.L = 15; 73 R7 = ASHIFT R0 BY R3.L (S); 74 R6 = ASHIFT R1 BY R3.L (S); 75 R5 = ASHIFT R2 BY R3.L (S); 76 R4 = ASHIFT R3 BY R3.L (S); 77 CHECKREG r4, 0x7FFFFFFF; 78 CHECKREG r5, 0x7FFFFFFF; 79 CHECKREG r6, 0x7FFFFFFF; 80 CHECKREG r7, 0x7FFFFFFF; 81 82 imm32 r0, 0x01230002; 83 imm32 r1, 0x12345678; 84 imm32 r2, 0x23456789; 85 imm32 r3, 0x3456789a; 86 imm32 r4, 0x456789ab; 87 imm32 r5, 0x56789abc; 88 imm32 r6, 0x6789abcd; 89 imm32 r7, 0x789abcde; 90 R4.L = -1; 91 R7 = ASHIFT R0 BY R4.L; 92 R0 = ASHIFT R1 BY R4.L; 93 R1 = ASHIFT R2 BY R4.L; 94 R2 = ASHIFT R3 BY R4.L; 95 R3 = ASHIFT R4 BY R4.L; 96 R4 = ASHIFT R5 BY R4.L; 97 R5 = ASHIFT R6 BY R4.L; 98 R6 = ASHIFT R7 BY R4.L; 99 CHECKREG r0, 0x091A2B3C; 100 CHECKREG r1, 0x11A2B3C4; 101 CHECKREG r2, 0x1A2B3C4D; 102 CHECKREG r3, 0x22B3FFFF; 103 CHECKREG r4, 0x2B3C4D5E; 104 CHECKREG r5, 0x40000000; 105 CHECKREG r6, 0x40000000; 106 CHECKREG r7, 0x00918001; 107 108 imm32 r0, 0x01230002; 109 imm32 r1, 0x82345678; 110 imm32 r2, 0x93456789; 111 imm32 r3, 0xa456789a; 112 imm32 r4, 0xb56789ab; 113 imm32 r5, 0xc6789abc; 114 imm32 r6, 0xd789abcd; 115 imm32 r7, 0xe89abcde; 116 R5.L = -6; 117 R6 = ASHIFT R0 BY R5.L (S); 118 R7 = ASHIFT R1 BY R5.L (S); 119 R0 = ASHIFT R2 BY R5.L (S); 120 R1 = ASHIFT R3 BY R5.L (S); 121 R2 = ASHIFT R4 BY R5.L (S); 122 R3 = ASHIFT R5 BY R5.L (S); 123 R4 = ASHIFT R6 BY R5.L (S); 124 R5 = ASHIFT R7 BY R5.L (S); 125 CHECKREG r0, 0xFE4D159E; 126 CHECKREG r1, 0xFE9159E2; 127 CHECKREG r2, 0xFED59E26; 128 CHECKREG r3, 0xFF19E3FF; 129 CHECKREG r4, 0x00001230; 130 CHECKREG r5, 0xFFF82345; 131 CHECKREG r6, 0x00048C00; 132 CHECKREG r7, 0xFE08D159; 133 134 imm32 r0, 0x01230002; 135 imm32 r1, 0x12345678; 136 imm32 r2, 0x23456789; 137 imm32 r3, 0x3456789a; 138 imm32 r4, 0x456789ab; 139 imm32 r5, 0x56789abc; 140 imm32 r6, 0x6789abcd; 141 imm32 r7, 0x789abcde; 142 R6.L = -15; 143 R5 = ASHIFT R0 BY R6.L (S); 144 R0 = ASHIFT R1 BY R6.L (S); 145 R7 = ASHIFT R2 BY R6.L (S); 146 R0 = ASHIFT R3 BY R6.L (S); 147 R1 = ASHIFT R4 BY R6.L (S); 148 R2 = ASHIFT R5 BY R6.L (S); 149 R3 = ASHIFT R6 BY R6.L (S); 150 R6 = ASHIFT R7 BY R6.L (S); 151 CHECKREG r0, 0x000068AC; 152 CHECKREG r1, 0x00008ACF; 153 CHECKREG r2, 0x00000000; 154 CHECKREG r3, 0x0000CF13; 155 CHECKREG r4, 0x456789AB; 156 CHECKREG r5, 0x00000246; 157 CHECKREG r6, 0x00000000; 158 CHECKREG r7, 0x0000468A; 159 160 imm32 r0, 0x01230002; 161 imm32 r1, 0x82345678; 162 imm32 r2, 0x93456789; 163 imm32 r3, 0xa456789a; 164 imm32 r4, 0xb56789ab; 165 imm32 r5, 0xc6789abc; 166 imm32 r6, 0xd789abcd; 167 imm32 r7, 0xe89abcde; 168 R7.L = -14; 169 R0 = ASHIFT R0 BY R7.L (S); 170 R1 = ASHIFT R1 BY R7.L (S); 171 R2 = ASHIFT R2 BY R7.L (S); 172 R3 = ASHIFT R3 BY R7.L (S); 173 R4 = ASHIFT R4 BY R7.L (S); 174 R5 = ASHIFT R5 BY R7.L (S); 175 R6 = ASHIFT R6 BY R7.L (S); 176 R7 = ASHIFT R7 BY R7.L (S); 177 CHECKREG r0, 0x0000048C; 178 CHECKREG r1, 0xFFFE08D1; 179 CHECKREG r2, 0xFFFE4D15; 180 CHECKREG r3, 0xFFFE9159; 181 CHECKREG r4, 0xFFFED59E; 182 CHECKREG r5, 0xFFFF19E2; 183 CHECKREG r6, 0xFFFF5E26; 184 CHECKREG r7, 0xFFFFA26B; 185 186 pass 187