1//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp 2// Spec Reference: dsp32mac pair a1 M MNOP 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 A1 = A0 = 0; 9 10// The result accumulated in A1 , and stored to a reg half 11 imm32 r0, 0x63547abd; 12 imm32 r1, 0x86bc8ec7; 13 imm32 r2, 0xa8695679; 14 imm32 r3, 0x00060007; 15 imm32 r4, 0xe6b86569; 16 imm32 r5, 0x1A35860b; 17 imm32 r6, 0x000c086d; 18 imm32 r7, 0x67Be0086; 19 R7 = ( A1 += R1.L * R0.L ); 20 P1 = A1.w; 21 R1 = ( A1 -= R2.H * R3.L ); 22 P2 = A1.w; 23 R3 = ( A1 = R7.L * R4.H ); 24 P3 = A1.w; 25 R5 = ( A1 += R6.H * R5.H ); 26 P4 = A1.w; 27 CHECKREG r0, 0x63547ABD; 28 CHECKREG r1, 0x93734818; 29 CHECKREG r2, 0xA8695679; 30 CHECKREG r3, 0xE7256BA0; 31 CHECKREG r4, 0xE6B86569; 32 CHECKREG r5, 0xE727E098; 33 CHECKREG r6, 0x000C086D; 34 CHECKREG r7, 0x936E7DD6; 35 CHECKREG p1, 0x936E7DD6; 36 CHECKREG p2, 0x93734818; 37 CHECKREG p3, 0xE7256BA0; 38 CHECKREG p4, 0xE727E098; 39 40 imm32 r0, 0x98764abd; 41 imm32 r1, 0xa1bcf4c7; 42 imm32 r2, 0xb1145649; 43 imm32 r3, 0x0b010005; 44 imm32 r4, 0xefbcbb69; 45 imm32 r5, 0x123501bb; 46 imm32 r6, 0x000c001b; 47 imm32 r7, 0x678e0001; 48 R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L; 49 P1 = A1.w; 50 R1 = ( A1 = R2.L * R3.H ) (M), A0 = R2.H * R3.L; 51 P2 = A1.w; 52 R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H; 53 P3 = A1.w; 54 R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H; 55 P4 = A1.w; 56 CHECKREG r0, 0x98764ABD; 57 CHECKREG r1, 0x3FE4AC0B; 58 CHECKREG r2, 0xB1145649; 59 CHECKREG r3, 0x3FD9C011; 60 CHECKREG r4, 0xEFBCBB69; 61 CHECKREG r5, 0xE078DC52; 62 CHECKREG r6, 0x000C001B; 63 CHECKREG r7, 0x678E0001; 64 CHECKREG p1, 0xE078DC52; 65 CHECKREG p2, 0x03B57949; 66 CHECKREG p3, 0x3FD9C011; 67 CHECKREG p4, 0x3FE4AC0B; 68 69 imm32 r0, 0x7136459d; 70 imm32 r1, 0xabd69ec7; 71 imm32 r2, 0x71145679; 72 imm32 r3, 0xd8010007; 73 imm32 r4, 0xeddc1569; 74 imm32 r5, 0x122d010b; 75 imm32 r6, 0x0003d01d; 76 imm32 r7, 0x678e0d61; 77 R5 = A1 , A0 = R1.L * R0.L; 78 P1 = A1.w; 79 R7 = A1 , A0 -= R2.H * R3.L; 80 P2 = A1.w; 81 R1 = A1 , A0 += R4.H * R5.H; 82 P3 = A1.w; 83 R5 = A1 , A0 += R6.L * R7.H; 84 P4 = A1.w; 85 CHECKREG r0, 0x7136459D; 86 CHECKREG r1, 0x3FE4AC0B; 87 CHECKREG r2, 0x71145679; 88 CHECKREG r3, 0xD8010007; 89 CHECKREG r4, 0xEDDC1569; 90 CHECKREG r5, 0x3FE4AC0B; 91 CHECKREG r6, 0x0003D01D; 92 CHECKREG r7, 0x3FE4AC0B; 93 CHECKREG p1, 0x3FE4AC0B; 94 CHECKREG p2, 0x3FE4AC0B; 95 CHECKREG p3, 0x3FE4AC0B; 96 CHECKREG p4, 0x3FE4AC0B; 97 98 imm32 r0, 0x123489bd; 99 imm32 r1, 0x91bcfec7; 100 imm32 r2, 0xa9145679; 101 imm32 r3, 0xd0910007; 102 imm32 r4, 0x34567899; 103 imm32 r5, 0xd235910b; 104 imm32 r6, 0x0d0c0999; 105 imm32 r7, 0x67de0009; 106 R1 = ( A1 += R5.H * R3.H ) (M); 107 P1 = A1.w; 108 R3 = ( A1 = R2.H * R1.H ) (M); 109 P2 = A1.w; 110 R5 = ( A1 -= R7.H * R0.H ) (M); 111 P3 = A1.w; 112 R7 = ( A1 += R4.H * R6.H ) (M); 113 P4 = A1.w; 114 CHECKREG r0, 0x123489BD; 115 CHECKREG r1, 0x1A95CC10; 116 CHECKREG r2, 0xA9145679; 117 CHECKREG r3, 0xF6F970A4; 118 CHECKREG r4, 0x34567899; 119 CHECKREG r5, 0xEF96BB8C; 120 CHECKREG r6, 0x0D0C0999; 121 CHECKREG r7, 0xF2418D94; 122 CHECKREG p1, 0x1A95CC10; 123 CHECKREG p2, 0xF6F970A4; 124 CHECKREG p3, 0xEF96BB8C; 125 CHECKREG p4, 0xF2418D94; 126 127 pass 128