1/* RISC-V simulator.
2
3   Copyright (C) 2005-2023 Free Software Foundation, Inc.
4   Contributed by Mike Frysinger.
5
6   This file is part of simulators.
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 3 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
21#ifndef SIM_MAIN_H
22#define SIM_MAIN_H
23
24#include "sim-basics.h"
25#include "machs.h"
26#include "sim-base.h"
27
28struct _sim_cpu {
29  union {
30    unsigned_word regs[32];
31    struct {
32      /* These are the ABI names.  */
33      unsigned_word zero, ra, sp, gp, tp;
34      unsigned_word t0, t1, t2;
35      unsigned_word s0, s1;
36      unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
37      unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
38      unsigned_word t3, t4, t5, t6;
39    };
40  };
41  union {
42    unsigned_word fpregs[32];
43    struct {
44      /* These are the ABI names.  */
45      unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
46      unsigned_word fs0, fs1;
47      unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
48      unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
49      unsigned_word ft8, ft9, ft10, ft11;
50    };
51  };
52  sim_cia pc;
53
54  struct {
55#define DECLARE_CSR(name, ...) unsigned_word name;
56#include "opcode/riscv-opc.h"
57#undef DECLARE_CSR
58  } csr;
59
60  sim_cpu_base base;
61};
62
63struct atomic_mem_reserved_list;
64struct atomic_mem_reserved_list {
65  struct atomic_mem_reserved_list *next;
66  address_word addr;
67};
68
69struct riscv_sim_state {
70  struct atomic_mem_reserved_list *amo_reserved_list;
71};
72#define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
73
74extern void step_once (SIM_CPU *);
75extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
76extern void initialize_env (SIM_DESC, const char * const *argv,
77			    const char * const *env);
78
79#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
80
81#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
82
83#endif
84